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From: Richard Henderson <richard.henderson@linaro.org>
To: Gan Qixin <ganqixin@huawei.com>,
	qemu-devel@nongnu.org, qemu-trivial@nongnu.org
Cc: kuhn.chenqun@huawei.com, Paolo Bonzini <pbonzini@redhat.com>,
	zhang.zhanghailiang@huawei.com,
	Euler Robot <euler.robot@huawei.com>
Subject: Re: [PATCH] util/cacheflush: Fix error generated by clang
Date: Fri, 15 Jan 2021 06:39:59 -1000	[thread overview]
Message-ID: <8d1971bb-0c0d-b7cb-5fed-4d105e17a511@linaro.org> (raw)
In-Reply-To: <20210115075656.717957-1-ganqixin@huawei.com>

On 1/14/21 9:56 PM, Gan Qixin wrote:
> When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following
> error:
> 
> ../util/cacheflush.c:38:44: error: value size does not match register size
> specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
>     asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
>                                            ^
> ../util/cacheflush.c:38:24: note: use constraint modifier "w"
>     asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
>                        ^~
>                        %w0
> 
> Modify the type of save_ctr_el0 to uint64_t to fix it.
> 
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Gan Qixin <ganqixin@huawei.com>
> ---
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  util/cacheflush.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

This is clang being overly-picky.  IMO it should have done the mrs into a
64-bit register, then truncated the value when storing to the 32-bit variable.
 Which is what GCC does.  Certainly the code as written only needs the low 20
bits of the result.

But your change will not really make any difference to the generated code,
except for 4 more bytes of storage, so:

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


  reply	other threads:[~2021-01-15 16:43 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-15  7:56 [PATCH] util/cacheflush: Fix error generated by clang Gan Qixin
2021-01-15 16:39 ` Richard Henderson [this message]
2021-01-17 16:43 ` Paolo Bonzini

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