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From: Bibo Mao <maobibo@loongson.cn>
To: Song Gao <gaosong@loongson.cn>
Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com
Subject: Re: [PATCH v6 10/11] target/loongarch:Implement csrrd CSR_MSGIR register
Date: Sat, 6 Sep 2025 15:20:59 +0800	[thread overview]
Message-ID: <8d4761a2-32db-eced-6f9a-d4b1e6acb397@loongson.cn> (raw)
In-Reply-To: <20250904121840.2023683-11-gaosong@loongson.cn>



On 2025/9/4 下午8:18, Song Gao wrote:
> implement the read-clear feature for CSR_MSGIR register.
> 
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/csr.c                        |  5 +++++
>   target/loongarch/tcg/csr_helper.c             | 21 +++++++++++++++++++
>   target/loongarch/tcg/helper.h                 |  1 +
>   .../tcg/insn_trans/trans_privileged.c.inc     |  1 +
>   4 files changed, 28 insertions(+)
> 
> diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
> index 7ea0a30450..f973780bba 100644
> --- a/target/loongarch/csr.c
> +++ b/target/loongarch/csr.c
> @@ -97,6 +97,11 @@ static CSRInfo csr_info[] = {
>       CSR_OFF(DBG),
>       CSR_OFF(DERA),
>       CSR_OFF(DSAVE),
> +    CSR_OFF_ARRAY(MSGIS, 0),
> +    CSR_OFF_ARRAY(MSGIS, 1),
> +    CSR_OFF_ARRAY(MSGIS, 2),
> +    CSR_OFF_ARRAY(MSGIS, 3),
> +    CSR_OFF(MSGIR),
>   };
>   
>   CSRInfo *get_csr(unsigned int csr_num)
> diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
> index 28b1bb86bd..347dca84b8 100644
> --- a/target/loongarch/tcg/csr_helper.c
> +++ b/target/loongarch/tcg/csr_helper.c
> @@ -72,6 +72,27 @@ target_ulong helper_csrrd_tval(CPULoongArchState *env)
>       return cpu_loongarch_get_constant_timer_ticks(cpu);
>   }
>   
> +target_ulong helper_csrrd_msgir(CPULoongArchState *env)
> +{
> +    int irq, new;
> +
> +    irq = find_first_bit(env->CSR_MSGIS, 256);
> +    if (irq < 256) {
> +        clear_bit(irq, env->CSR_MSGIS);
> +        new = find_first_bit(env->CSR_MSGIS, 256);
> +        if (new < 256) {
> +            return irq;
> +        }
> +
> +        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0);
> +    } else {
> +        /* bit 31 set 1 for no invalid irq */
> +        irq = BIT(31);
> +    }
> +
> +    return irq;
> +}
> +
>   target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)
>   {
>       int64_t old_v = env->CSR_ESTAT;
> diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h
> index 1d5cb0198c..db57dbfc16 100644
> --- a/target/loongarch/tcg/helper.h
> +++ b/target/loongarch/tcg/helper.h
> @@ -100,6 +100,7 @@ DEF_HELPER_1(rdtime_d, i64, env)
>   DEF_HELPER_1(csrrd_pgd, i64, env)
>   DEF_HELPER_1(csrrd_cpuid, i64, env)
>   DEF_HELPER_1(csrrd_tval, i64, env)
> +DEF_HELPER_1(csrrd_msgir, i64, env)
>   DEF_HELPER_2(csrwr_stlbps, i64, env, tl)
>   DEF_HELPER_2(csrwr_estat, i64, env, tl)
>   DEF_HELPER_2(csrwr_asid, i64, env, tl)
> diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
> index 34cfab8879..a407ab51b7 100644
> --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
> @@ -83,6 +83,7 @@ void loongarch_csr_translate_init(void)
>       SET_CSR_FUNC(TCFG,  NULL, gen_helper_csrwr_tcfg);
>       SET_CSR_FUNC(TVAL,  gen_helper_csrrd_tval, NULL);
>       SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr);
> +    SET_CSR_FUNC(MSGIR, gen_helper_csrrd_msgir, NULL);
>   }
>   #undef SET_CSR_FUNC
>   
> 
Reviewed-by: Bibo Mao <maobibo@loongson.cn>



  reply	other threads:[~2025-09-06  7:24 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-04 12:18 [PATCH v6 00/11] hw/loongarch: add the advanced extended interrupt controllers (AVECINTC) support Song Gao
2025-09-04 12:18 ` [PATCH v6 01/11] target/loongarch: move some machine define to virt.h Song Gao
2025-09-04 12:18 ` [PATCH v6 02/11] hw/loongarch: add virt feature avecintc support Song Gao
2025-09-05  8:35   ` Bibo Mao
2025-09-04 12:18 ` [PATCH v6 03/11] hw/loongarch: add misc register supoort avecintc Song Gao
2025-09-05  8:40   ` Bibo Mao
2025-09-06  1:42     ` gaosong
2025-09-04 12:18 ` [PATCH v6 04/11] loongarch: add a advance interrupt controller device Song Gao
2025-09-05  8:44   ` Bibo Mao
2025-09-04 12:18 ` [PATCH v6 05/11] target/loongarch: add msg interrupt CSR registers Song Gao
2025-09-05  8:55   ` Bibo Mao
2025-09-06  2:22     ` gaosong
2025-09-04 12:18 ` [PATCH v6 06/11] hw/loongarch: AVEC controller add a MemoryRegion Song Gao
2025-09-05  8:58   ` Bibo Mao
2025-09-04 12:18 ` [PATCH v6 07/11] hw/loongarch: Implement avec controller imput and output pins Song Gao
2025-09-05  9:15   ` Bibo Mao
2025-09-04 12:18 ` [PATCH v6 08/11] hw/loongarch: Implement avec set irq Song Gao
2025-09-05  9:52   ` Bibo Mao
2025-09-06  8:26     ` gaosong
2025-09-05 10:05   ` Bibo Mao
2025-09-06  7:13     ` Bibo Mao
2025-09-06  8:33       ` gaosong
2025-09-04 12:18 ` [PATCH v6 09/11] target/loongarch: Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for msg interrupts Song Gao
2025-09-06  7:18   ` Bibo Mao
2025-09-04 12:18 ` [PATCH v6 10/11] target/loongarch:Implement csrrd CSR_MSGIR register Song Gao
2025-09-06  7:20   ` Bibo Mao [this message]
2025-09-04 12:18 ` [PATCH v6 11/11] hw/loongarch: Implement AVEC plug/unplug interfaces Song Gao
2025-09-06  7:22   ` Bibo Mao

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