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[88.21.102.131]) by smtp.gmail.com with ESMTPSA id u26sm24287wmj.9.2019.11.18.09.13.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Nov 2019 09:13:21 -0800 (PST) Subject: Re: [PATCH v35 00/13] QEMU AVR 8 bit cores To: Michael Rolnik , qemu-devel@nongnu.org, Joaquin de Andres References: <20191029212430.20617-1-mrolnik@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <8d4b6ae5-68c4-546a-2d1d-e12c95176cb6@redhat.com> Date: Mon, 18 Nov 2019 18:13:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191029212430.20617-1-mrolnik@gmail.com> Content-Language: en-US X-MC-Unique: Ygmxa2wrMbOc1iSTQG8pgQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, richard.henderson@linaro.org, Sarah Harris , dovgaluk@ispras.ru, imammedo@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Michael, Joaquin. Michael: Joaquin asked at the KVM Forum how he can start contributing to=20 QEMU, having an electronic background, and being custom the the AVR=20 microprocessor. I told him about your ongoing work. Joaquin is=20 interested in adding a new board to QEMU, and the Arduino would be his=20 board of choice. Joaquin: This is the series I was tell you about. This series will=20 likely be merged during the 5.0 development window. It lacks a real=20 hardware model. Michael and Sarah didn't wrote one because they focus on=20 the architecture part, which is enough for them (to test that AVR GCC). See below for more comments about the codebase organization. On 10/29/19 10:24 PM, Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully te= sted yet. > However I was able to execute simple code with functions. e.g fibonacci c= alculation. > This series of patches include a non real, sample board. > No fuses support yet. PC is set to 0 at reset. >=20 > the patches include the following > 1. just a basic 8bit AVR CPU, without instruction decoding or translation > 2. CPU features which allow define the following 8bit AVR cores > avr1 > avr2 avr25 > avr3 avr31 avr35 > avr4 > avr5 avr51 > avr6 > xmega2 xmega4 xmega5 xmega6 xmega7 > 3. a definition of sample machine with SRAM, FLASH and CPU which allows t= o execute simple code > 4. encoding for all AVR instructions > 5. interrupt handling > 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions > 7. a decoder which given an opcode decides what istruction it is > 8. translation of AVR instruction into TCG > 9. all features together [...] > MAINTAINERS | 9 + > arch_init.c | 2 + > configure | 7 + > default-configs/avr-softmmu.mak | 5 + > gdb-xml/avr-cpu.xml | 49 + The part under hw/avr/ is the 'board' part. You can take a AVR cpu, glue it with peripherals (mapping blocks and=20 wiring IRQ), put it on a PCB ('board') and connect external devices. You get a QEMU machine. You can load a ELF program directly to memory=20 and execute it, or you can load a firmware from ROM/flash. > hw/Kconfig | 1 + > hw/avr/Kconfig = | 6 + > hw/avr/Makefile.objs | 1 + > hw/avr/sample.c | 282 +++ > hw/char/Kconfig | 3 + > hw/char/Makefile.objs | 1 + > hw/char/avr_usart.c | 324 ++++ > hw/misc/Kconfig | 3 + > hw/misc/Makefile.objs | 2 + > hw/misc/avr_mask.c | 112 ++ > hw/timer/Kconfig | 3 + > hw/timer/Makefile.objs | 2 + > hw/timer/avr_timer16.c | 605 ++++++ > include/disas/dis-asm.h | 6 + > include/hw/char/avr_usart.h | 97 + > include/hw/misc/avr_mask.h | 47 + > include/hw/timer/avr_timer16.h | 97 + > include/sysemu/arch_init.h | 1 + > qapi/machine.json | 3 +- The files under target/avr/ are the architecture part. Michael and Sarah run the GCC test suite on this, so this part should be=20 quite correct and you shouldn't worry about looking here, except if some=20 instruction behaves incorrectly. I strongly suggest you to stay focused=20 with the files under hw/ and include/hw/. > target/avr/Makefile.objs | 33 + > target/avr/cpu-param.h | 37 + > target/avr/cpu-qom.h | 54 + > target/avr/cpu.c | 576 ++++++ > target/avr/cpu.h | 253 +++ > target/avr/gdbstub.c | 85 + > target/avr/helper.c | 354 ++++ > target/avr/helper.h | 29 + > target/avr/insn.decode | 175 ++ > target/avr/machine.c | 121 ++ > target/avr/translate.c | 3028 ++++++++++++++++++++++++++++++ > tests/Makefile.include | 2 + > tests/acceptance/machine_avr6.py | 36 + > tests/boot-serial-test.c | 10 + > tests/machine-none-test.c | 1 + > 39 files changed, 6461 insertions(+), 1 deletion(-) Hope this helps a bit to start looking at QEMU. You are welcome to ask any question on this list or on IRC. Regards, Phil.