From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 091/163] tcg: Convert bswap64 to TCGOutOpUnary
Date: Tue, 15 Apr 2025 14:48:32 -0700 [thread overview]
Message-ID: <8d6bbc6b-280f-4f76-a3be-0a5cd64b8e96@linaro.org> (raw)
In-Reply-To: <20250415192515.232910-92-richard.henderson@linaro.org>
On 4/15/25 12:24, Richard Henderson wrote:
> Use TCGOutOpUnary instead of TCGOutOpBswap because the
> flags are not used with this opcode; they are merely
> present for uniformity with the smaller bswaps.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target-has.h | 1 -
> tcg/i386/tcg-target-has.h | 1 -
> tcg/loongarch64/tcg-target-has.h | 1 -
> tcg/mips/tcg-target-has.h | 1 -
> tcg/ppc/tcg-target-has.h | 1 -
> tcg/riscv/tcg-target-has.h | 1 -
> tcg/s390x/tcg-target-has.h | 1 -
> tcg/sparc64/tcg-target-has.h | 1 -
> tcg/tcg-has.h | 1 -
> tcg/tci/tcg-target-has.h | 1 -
> tcg/tcg-op.c | 2 +-
> tcg/tcg.c | 7 ++-
> tcg/tci.c | 2 -
> tcg/aarch64/tcg-target.c.inc | 15 ++++--
> tcg/arm/tcg-target.c.inc | 4 ++
> tcg/i386/tcg-target.c.inc | 16 ++++--
> tcg/loongarch64/tcg-target.c.inc | 15 ++++--
> tcg/mips/tcg-target.c.inc | 37 ++++++++------
> tcg/ppc/tcg-target.c.inc | 88 ++++++++++++++++----------------
> tcg/riscv/tcg-target.c.inc | 16 ++++--
> tcg/s390x/tcg-target.c.inc | 15 ++++--
> tcg/sparc64/tcg-target.c.inc | 4 ++
> tcg/tci/tcg-target.c.inc | 17 ++++--
> 23 files changed, 144 insertions(+), 104 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
> index 7c3d3fc637..82d8cd5965 100644
> --- a/tcg/aarch64/tcg-target-has.h
> +++ b/tcg/aarch64/tcg-target-has.h
> @@ -19,7 +19,6 @@
> #define TCG_TARGET_HAS_extr_i64_i32 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> -#define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h
> index ca533ab5cf..6b91b23fe8 100644
> --- a/tcg/i386/tcg-target-has.h
> +++ b/tcg/i386/tcg-target-has.h
> @@ -33,7 +33,6 @@
> #if TCG_TARGET_REG_BITS == 64
> /* Keep 32-bit values zero-extended in a register. */
> #define TCG_TARGET_HAS_extr_i64_i32 1
> -#define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h
> index e66df31954..10090102f7 100644
> --- a/tcg/loongarch64/tcg-target-has.h
> +++ b/tcg/loongarch64/tcg-target-has.h
> @@ -18,7 +18,6 @@
> /* 64-bit operations */
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_extr_i64_i32 1
> -#define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_add2_i64 0
> #define TCG_TARGET_HAS_sub2_i64 0
>
> diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
> index 2391f5d8bf..24b00f1eec 100644
> --- a/tcg/mips/tcg-target-has.h
> +++ b/tcg/mips/tcg-target-has.h
> @@ -55,7 +55,6 @@ extern bool use_mips32r2_instructions;
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #if TCG_TARGET_REG_BITS == 64
> -#define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 0
> #endif
>
> diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
> index ad0885d635..bd9c3d92ed 100644
> --- a/tcg/ppc/tcg-target-has.h
> +++ b/tcg/ppc/tcg-target-has.h
> @@ -24,7 +24,6 @@
> #define TCG_TARGET_HAS_add2_i32 0
> #define TCG_TARGET_HAS_sub2_i32 0
> #define TCG_TARGET_HAS_extr_i64_i32 0
> -#define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
> index fbe294474a..88fadc2428 100644
> --- a/tcg/riscv/tcg-target-has.h
> +++ b/tcg/riscv/tcg-target-has.h
> @@ -17,7 +17,6 @@
>
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_extr_i64_i32 1
> -#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
>
> diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h
> index 76cfe4f323..95407f61cf 100644
> --- a/tcg/s390x/tcg-target-has.h
> +++ b/tcg/s390x/tcg-target-has.h
> @@ -35,7 +35,6 @@ extern uint64_t s390_facilities[3];
> #define TCG_TARGET_HAS_extr_i64_i32 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> -#define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h
> index 22837beca9..2ced6f7c1c 100644
> --- a/tcg/sparc64/tcg-target-has.h
> +++ b/tcg/sparc64/tcg-target-has.h
> @@ -20,7 +20,6 @@ extern bool use_vis3_instructions;
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #define TCG_TARGET_HAS_extr_i64_i32 0
> -#define TCG_TARGET_HAS_bswap64_i64 0
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h
> index 4034c73cca..21bef070fe 100644
> --- a/tcg/tcg-has.h
> +++ b/tcg/tcg-has.h
> @@ -12,7 +12,6 @@
> #if TCG_TARGET_REG_BITS == 32
> /* Turn some undef macros into false macros. */
> #define TCG_TARGET_HAS_extr_i64_i32 0
> -#define TCG_TARGET_HAS_bswap64_i64 0
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_add2_i64 0
> #define TCG_TARGET_HAS_sub2_i64 0
> diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
> index c5c64f4f5d..90aa5c8bbb 100644
> --- a/tcg/tci/tcg-target-has.h
> +++ b/tcg/tci/tcg-target-has.h
> @@ -12,7 +12,6 @@
>
> #if TCG_TARGET_REG_BITS == 64
> #define TCG_TARGET_HAS_extr_i64_i32 0
> -#define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index b1174f60cc..27e700161f 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -2184,7 +2184,7 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
> tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
> tcg_temp_free_i32(t0);
> tcg_temp_free_i32(t1);
> - } else if (TCG_TARGET_HAS_bswap64_i64) {
> + } else if (tcg_op_supported(INDEX_op_bswap64_i64, TCG_TYPE_I64, 0)) {
> tcg_gen_op3i_i64(INDEX_op_bswap64_i64, ret, arg, 0);
> } else {
> TCGv_i64 t0 = tcg_temp_ebb_new_i64();
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 51f9cc7fe1..3031582174 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1112,6 +1112,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
> #if TCG_TARGET_REG_BITS == 32
> OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2),
> OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2),
> +#else
> + OUTOP(INDEX_op_bswap64_i64, TCGOutOpUnary, outop_bswap64),
> #endif
> };
>
> @@ -2371,8 +2373,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extrl_i64_i32:
> case INDEX_op_extrh_i64_i32:
> return TCG_TARGET_HAS_extr_i64_i32;
> - case INDEX_op_bswap64_i64:
> - return TCG_TARGET_HAS_bswap64_i64;
> case INDEX_op_add2_i64:
> return TCG_TARGET_HAS_add2_i64;
> case INDEX_op_sub2_i64:
> @@ -5467,6 +5467,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> }
> break;
>
> + case INDEX_op_bswap64_i64:
> + assert(TCG_TARGET_REG_BITS == 64);
> + /* fall through */
> case INDEX_op_ctpop:
> case INDEX_op_neg:
> case INDEX_op_not:
> diff --git a/tcg/tci.c b/tcg/tci.c
> index f98c437100..903f996f02 100644
> --- a/tcg/tci.c
> +++ b/tcg/tci.c
> @@ -788,12 +788,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> tci_args_rr(insn, &r0, &r1);
> regs[r0] = (uint32_t)regs[r1];
> break;
> -#if TCG_TARGET_HAS_bswap64_i64
> case INDEX_op_bswap64_i64:
> tci_args_rr(insn, &r0, &r1);
> regs[r0] = bswap64(regs[r1]);
> break;
> -#endif
> #endif /* TCG_TARGET_REG_BITS == 64 */
>
> /* QEMU specific operations. */
> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
> index a2e45ca5c8..79c0e2e097 100644
> --- a/tcg/aarch64/tcg-target.c.inc
> +++ b/tcg/aarch64/tcg-target.c.inc
> @@ -2470,6 +2470,16 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
> +}
> +
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_bswap64,
> +};
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tgen_sub(s, type, a0, TCG_REG_XZR, a1);
> @@ -2637,10 +2647,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
> tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false);
> break;
>
> - case INDEX_op_bswap64_i64:
> - tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
> - break;
> -
> case INDEX_op_deposit_i64:
> case INDEX_op_deposit_i32:
> tcg_out_dep(s, ext, a0, a2, args[3], args[4]);
> @@ -3159,7 +3165,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld32u_i64:
> case INDEX_op_ld32s_i64:
> case INDEX_op_ld_i64:
> - case INDEX_op_bswap64_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> case INDEX_op_extract_i32:
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index 4ca23bb718..3bbc28c63c 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -2163,6 +2163,10 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tgen_subfi(s, type, a0, 0, a1);
> diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
> index 6d90666ba7..347e01c076 100644
> --- a/tcg/i386/tcg-target.c.inc
> +++ b/tcg/i386/tcg-target.c.inc
> @@ -3104,6 +3104,18 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +#if TCG_TARGET_REG_BITS == 64
> +static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + tcg_out_bswap64(s, a0);
> +}
> +
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_O1_I1(r, 0),
> + .out_rr = tgen_bswap64,
> +};
> +#endif
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
> @@ -3279,9 +3291,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - case INDEX_op_bswap64_i64:
> - tcg_out_bswap64(s, a0);
> - break;
> case INDEX_op_extrh_i64_i32:
> tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32);
> break;
> @@ -3979,7 +3988,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st_i64:
> return C_O0_I2(re, r);
>
> - case INDEX_op_bswap64_i64:
> case INDEX_op_extrh_i64_i32:
> return C_O1_I1(r, 0);
>
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index e518cd9477..25adbb0609 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1757,6 +1757,16 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + tcg_out_opc_revb_d(s, a0, a1);
> +}
> +
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_bswap64,
> +};
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
> @@ -1848,10 +1858,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
> break;
>
> - case INDEX_op_bswap64_i64:
> - tcg_out_opc_revb_d(s, a0, a1);
> - break;
> -
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld8s_i64:
> tcg_out_ldst(s, OPC_LD_B, a0, a1, a2);
> @@ -2453,7 +2459,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> - case INDEX_op_bswap64_i64:
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld8s_i64:
> case INDEX_op_ld8u_i32:
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index ab8f8c9994..baaf0e416b 100644
> --- a/tcg/mips/tcg-target.c.inc
> +++ b/tcg/mips/tcg-target.c.inc
> @@ -710,19 +710,6 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
> }
> }
>
> -static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
> -{
> - if (use_mips32r2_instructions) {
> - tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
> - tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
> - } else {
> - tcg_out_bswap_subr(s, bswap64_addr);
> - /* delay slot -- never omit the insn, like tcg_out_mov might. */
> - tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
> - tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
> - }
> -}
> -
> static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
> {
> tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
> @@ -2176,6 +2163,26 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +#if TCG_TARGET_REG_BITS == 64
> +static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> +{
> + if (use_mips32r2_instructions) {
> + tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
> + tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
> + } else {
> + tcg_out_bswap_subr(s, bswap64_addr);
> + /* delay slot -- never omit the insn, like tcg_out_mov might. */
> + tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
> + tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
> + }
> +}
> +
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_bswap64,
> +};
> +#endif /* TCG_TARGET_REG_BITS == 64 */
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
> @@ -2267,9 +2274,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_ldst(s, i1, a0, a1, a2);
> break;
>
> - case INDEX_op_bswap64_i64:
> - tcg_out_bswap64(s, a0, a1);
> - break;
> case INDEX_op_extrh_i64_i32:
> tcg_out_dsra(s, a0, a1, 32);
> break;
> @@ -2380,7 +2384,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld32s_i64:
> case INDEX_op_ld32u_i64:
> case INDEX_op_ld_i64:
> - case INDEX_op_bswap64_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> case INDEX_op_extrl_i64_i32:
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index 4527ed3eee..083137d211 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -1012,44 +1012,6 @@ static void tcg_out_addpcis(TCGContext *s, TCGReg dst, intptr_t imm)
> tcg_out32(s, ADDPCIS | RT(dst) | (d1 << 16) | (d0 << 6) | d2);
> }
>
> -static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src)
> -{
> - TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
> - TCGReg t1 = dst == src ? dst : TCG_REG_R0;
> -
> - if (have_isa_3_10) {
> - tcg_out32(s, BRD | RA(dst) | RS(src));
> - return;
> - }
> -
> - /*
> - * In the following,
> - * dep(a, b, m) -> (a & ~m) | (b & m)
> - *
> - * Begin with: src = abcdefgh
> - */
> - /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */
> - tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31);
> - /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */
> - tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7);
> - /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */
> - tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23);
> -
> - /* t0 = rol64(t0, 32) = hgfe0000 */
> - tcg_out_rld(s, RLDICL, t0, t0, 32, 0);
> - /* t1 = rol64(src, 32) = efghabcd */
> - tcg_out_rld(s, RLDICL, t1, src, 32, 0);
> -
> - /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */
> - tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31);
> - /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */
> - tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7);
> - /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */
> - tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23);
> -
> - tcg_out_mov(s, TCG_TYPE_REG, dst, t0);
> -}
> -
> /* Emit a move into ret of arg, if it can be done in one insn. */
> static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
> {
> @@ -3390,6 +3352,51 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +#if TCG_TARGET_REG_BITS == 64
> +static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
> +{
> + TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
> + TCGReg t1 = dst == src ? dst : TCG_REG_R0;
> +
> + if (have_isa_3_10) {
> + tcg_out32(s, BRD | RA(dst) | RS(src));
> + return;
> + }
> +
> + /*
> + * In the following,
> + * dep(a, b, m) -> (a & ~m) | (b & m)
> + *
> + * Begin with: src = abcdefgh
> + */
> + /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */
> + tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31);
> + /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */
> + tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7);
> + /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */
> + tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23);
> +
> + /* t0 = rol64(t0, 32) = hgfe0000 */
> + tcg_out_rld(s, RLDICL, t0, t0, 32, 0);
> + /* t1 = rol64(src, 32) = efghabcd */
> + tcg_out_rld(s, RLDICL, t1, src, 32, 0);
> +
> + /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */
> + tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31);
> + /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */
> + tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7);
> + /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */
> + tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23);
> +
> + tcg_out_mov(s, TCG_TYPE_REG, dst, t0);
> +}
> +
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_bswap64,
> +};
> +#endif /* TCG_TARGET_REG_BITS == 64 */
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tcg_out32(s, NEG | RT(a0) | RA(a1));
> @@ -3512,10 +3519,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
> break;
>
> - case INDEX_op_bswap64_i64:
> - tcg_out_bswap64(s, args[0], args[1]);
> - break;
> -
> case INDEX_op_deposit_i32:
> if (const_args[2]) {
> uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
> @@ -4263,7 +4266,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> - case INDEX_op_bswap64_i64:
> case INDEX_op_extract_i64:
> case INDEX_op_sextract_i64:
> return C_O1_I1(r, r);
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 9b6ca54ae7..00b097d171 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -2441,6 +2441,17 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
> +}
> +
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_Dynamic,
> + .base.dynamic_constraint = cset_bswap,
> + .out_rr = tgen_bswap64,
> +};
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
> @@ -2523,10 +2534,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_ldst(s, OPC_SD, a0, a1, a2);
> break;
>
> - case INDEX_op_bswap64_i64:
> - tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
> - break;
> -
> case INDEX_op_add2_i32:
> tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
> const_args[4], const_args[5], false, true);
> @@ -2864,7 +2871,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> - case INDEX_op_bswap64_i64:
> return C_O1_I1(r, r);
>
> case INDEX_op_st8_i32:
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index ed2da3f31d..2ed288cfe0 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -2776,6 +2776,16 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + tcg_out_insn(s, RRE, LRVGR, a0, a1);
> +}
> +
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_bswap64,
> +};
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> if (type == TCG_TYPE_I32) {
> @@ -2922,10 +2932,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
> break;
>
> - case INDEX_op_bswap64_i64:
> - tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
> - break;
> -
> case INDEX_op_add2_i64:
> if (const_args[4]) {
> if ((int64_t)args[4] >= 0) {
> @@ -3462,7 +3468,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st_i64:
> return C_O0_I2(r, r);
>
> - case INDEX_op_bswap64_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> case INDEX_op_extract_i32:
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index cbe9c759ec..96ffba9af6 100644
> --- a/tcg/sparc64/tcg-target.c.inc
> +++ b/tcg/sparc64/tcg-target.c.inc
> @@ -1733,6 +1733,10 @@ static const TCGOutOpBswap outop_bswap32 = {
> .base.static_constraint = C_NotImplemented,
> };
>
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tgen_sub(s, type, a0, TCG_REG_G0, a1);
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 7478ada393..cbfe92adf3 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -57,7 +57,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> - case INDEX_op_bswap64_i64:
> case INDEX_op_extract_i32:
> case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> @@ -928,6 +927,18 @@ static const TCGOutOpBswap outop_bswap32 = {
> .out_rr = tgen_bswap32,
> };
>
> +#if TCG_TARGET_REG_BITS == 64
> +static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + tcg_out_op_rr(s, INDEX_op_bswap64_i64, a0, a1);
> +}
> +
> +static const TCGOutOpUnary outop_bswap64 = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_bswap64,
> +};
> +#endif
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tcg_out_op_rr(s, INDEX_op_neg, a0, a1);
> @@ -1072,10 +1083,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_op_rrbb(s, opc, args[0], args[1], args[2], args[3]);
> break;
>
> - case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
> - tcg_out_op_rr(s, opc, args[0], args[1]);
> - break;
> -
> CASE_32_64(add2)
> CASE_32_64(sub2)
> tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2025-04-15 21:49 UTC|newest]
Thread overview: 316+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 19:22 [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Richard Henderson
2025-04-15 19:22 ` [PATCH v4 001/163] tcg: Add all_outop[] Richard Henderson
2025-04-15 19:22 ` [PATCH v4 002/163] tcg: Use extract2 for cross-word 64-bit extract on 32-bit host Richard Henderson
2025-04-15 19:22 ` [PATCH v4 003/163] tcg: Remove INDEX_op_ext{8,16,32}* Richard Henderson
2025-04-15 19:22 ` [PATCH v4 004/163] tcg: Merge INDEX_op_mov_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 005/163] tcg: Convert add to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 006/163] tcg: Merge INDEX_op_add_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 007/163] tcg: Convert and to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 008/163] tcg: Merge INDEX_op_and_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 009/163] tcg/optimize: Fold andc with immediate to and Richard Henderson
2025-04-15 19:22 ` [PATCH v4 010/163] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2 Richard Henderson
2025-04-15 19:22 ` [PATCH v4 011/163] tcg: Convert andc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 012/163] tcg: Merge INDEX_op_andc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 013/163] tcg: Convert or to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 014/163] tcg: Merge INDEX_op_or_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 015/163] tcg/optimize: Fold orc with immediate to or Richard Henderson
2025-04-15 19:22 ` [PATCH v4 016/163] tcg: Convert orc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 017/163] tcg: Merge INDEX_op_orc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 018/163] tcg: Convert xor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 019/163] tcg: Merge INDEX_op_xor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 020/163] tcg/optimize: Fold eqv with immediate to xor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 021/163] tcg: Convert eqv to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 022/163] tcg: Merge INDEX_op_eqv_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 023/163] tcg: Convert nand to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 024/163] tcg: Merge INDEX_op_nand_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 025/163] tcg/loongarch64: Do not accept constant argument to nor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 026/163] tcg: Convert nor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 027/163] tcg: Merge INDEX_op_nor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 028/163] tcg/arm: Fix constraints for sub Richard Henderson
2025-04-15 19:23 ` [PATCH v4 029/163] tcg: Convert sub to TCGOutOpSubtract Richard Henderson
2025-04-15 21:00 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 030/163] tcg: Merge INDEX_op_sub_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 031/163] tcg: Convert neg to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 032/163] tcg: Merge INDEX_op_neg_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 033/163] tcg: Convert not to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 034/163] tcg: Merge INDEX_op_not_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 035/163] tcg: Convert mul to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 036/163] tcg: Merge INDEX_op_mul_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 037/163] tcg: Convert muluh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 038/163] tcg: Merge INDEX_op_muluh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 039/163] tcg: Convert mulsh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 040/163] tcg: Merge INDEX_op_mulsh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 041/163] tcg: Convert div to TCGOutOpBinary Richard Henderson
2025-04-15 21:02 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 042/163] tcg: Merge INDEX_op_div_{i32,i64} Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-22 15:27 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 043/163] tcg: Convert divu to TCGOutOpBinary Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 044/163] tcg: Merge INDEX_op_divu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 045/163] tcg: Convert div2 to TCGOutOpDivRem Richard Henderson
2025-04-15 19:23 ` [PATCH v4 046/163] tcg: Merge INDEX_op_div2_{i32,i64} Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 047/163] tcg: Convert divu2 to TCGOutOpDivRem Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 048/163] tcg: Merge INDEX_op_divu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 049/163] tcg: Convert rem to TCGOutOpBinary Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 050/163] tcg: Merge INDEX_op_rem_{i32,i64} Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 051/163] tcg: Convert remu to TCGOutOpBinary Richard Henderson
2025-04-15 21:07 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 052/163] tcg: Merge INDEX_op_remu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 053/163] tcg: Convert shl to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 054/163] tcg: Merge INDEX_op_shl_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 055/163] tcg: Convert shr to TCGOutOpBinary Richard Henderson
2025-04-15 21:08 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 056/163] tcg: Merge INDEX_op_shr_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary Richard Henderson
2025-04-15 21:09 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 058/163] tcg: Merge INDEX_op_sar_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 059/163] tcg: Do not require both rotr and rotl from the backend Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 060/163] tcg: Convert rotl, rotr to TCGOutOpBinary Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 061/163] tcg: Merge INDEX_op_rot{l,r}_{i32,i64} Richard Henderson
2025-04-15 21:11 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 062/163] tcg: Convert clz to TCGOutOpBinary Richard Henderson
2025-04-15 21:12 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 063/163] tcg: Merge INDEX_op_clz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 064/163] tcg: Convert ctz to TCGOutOpBinary Richard Henderson
2025-04-15 21:13 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 065/163] tcg: Merge INDEX_op_ctz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 066/163] tcg: Convert ctpop to TCGOutOpUnary Richard Henderson
2025-04-15 21:14 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 067/163] tcg: Merge INDEX_op_ctpop_{i32,i64} Richard Henderson
2025-04-15 21:15 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 068/163] tcg: Convert muls2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 069/163] tcg: Merge INDEX_op_muls2_{i32,i64} Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 070/163] tcg: Convert mulu2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:18 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 071/163] tcg: Merge INDEX_op_mulu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 072/163] tcg/loongarch64: Support negsetcond Richard Henderson
2025-04-15 21:19 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 073/163] tcg/mips: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 074/163] tcg/tci: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-22 15:28 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 075/163] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64} Richard Henderson
2025-04-22 15:35 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 076/163] tcg: Convert setcond, negsetcond to TCGOutOpSetcond Richard Henderson
2025-04-15 21:21 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 077/163] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}` Richard Henderson
2025-04-15 21:22 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 078/163] tcg: Convert brcond to TCGOutOpBrcond Richard Henderson
2025-04-15 21:23 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 079/163] tcg: Merge INDEX_op_brcond_{i32,i64} Richard Henderson
2025-04-15 21:24 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 080/163] tcg: Convert movcond to TCGOutOpMovcond Richard Henderson
2025-04-15 21:25 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 081/163] tcg: Merge INDEX_op_movcond_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 082/163] tcg/ppc: Drop fallback constant loading in tcg_out_cmp Richard Henderson
2025-04-15 21:26 ` Pierrick Bouvier
2025-04-16 14:39 ` Nicholas Piggin
2025-04-16 18:57 ` Richard Henderson
2025-04-15 19:23 ` [PATCH v4 083/163] tcg/arm: Expand arguments to tcg_out_cmp2 Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 084/163] tcg/ppc: " Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-16 14:43 ` Nicholas Piggin
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 085/163] tcg: Convert brcond2_i32 to TCGOutOpBrcond2 Richard Henderson
2025-04-15 21:37 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 086/163] tcg: Convert setcond2_i32 to TCGOutOpSetcond2 Richard Henderson
2025-04-15 21:39 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 087/163] tcg: Convert bswap16 to TCGOutOpBswap Richard Henderson
2025-04-15 21:40 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 088/163] tcg: Merge INDEX_op_bswap16_{i32,i64} Richard Henderson
2025-04-15 21:41 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 089/163] tcg: Convert bswap32 to TCGOutOpBswap Richard Henderson
2025-04-15 21:46 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 090/163] tcg: Merge INDEX_op_bswap32_{i32,i64} Richard Henderson
2025-04-15 21:47 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 091/163] tcg: Convert bswap64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier [this message]
2025-04-15 19:24 ` [PATCH v4 092/163] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64 Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 093/163] tcg: Convert extract to TCGOutOpExtract Richard Henderson
2025-04-15 21:50 ` Pierrick Bouvier
2025-06-09 13:52 ` Andrea Bolognani
2025-06-26 16:20 ` Andrea Bolognani
2025-06-27 13:16 ` Richard Henderson
2025-06-27 14:29 ` Philippe Mathieu-Daudé
2025-06-30 12:08 ` Andrea Bolognani
2025-04-15 19:24 ` [PATCH v4 094/163] tcg: Merge INDEX_op_extract_{i32,i64} Richard Henderson
2025-04-15 21:51 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 095/163] tcg: Convert sextract to TCGOutOpExtract Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 096/163] tcg: Merge INDEX_op_sextract_{i32,i64} Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 097/163] tcg: Convert ext_i32_i64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 098/163] tcg: Convert extu_i32_i64 " Richard Henderson
2025-04-15 21:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 099/163] tcg: Convert extrl_i64_i32 " Richard Henderson
2025-04-15 21:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 100/163] tcg: Convert extrh_i64_i32 " Richard Henderson
2025-04-15 21:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 101/163] tcg: Convert deposit to TCGOutOpDeposit Richard Henderson
2025-04-15 21:59 ` Pierrick Bouvier
2025-08-28 7:37 ` Michael Tokarev
2025-04-15 19:24 ` [PATCH v4 102/163] tcg/aarch64: Improve deposit Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 103/163] tcg: Merge INDEX_op_deposit_{i32,i64} Richard Henderson
2025-04-15 19:24 ` [PATCH v4 104/163] tcg: Convert extract2 to TCGOutOpExtract2 Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 105/163] tcg: Merge INDEX_op_extract2_{i32,i64} Richard Henderson
2025-04-15 22:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 106/163] tcg: Expand fallback add2 with 32-bit operations Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 107/163] tcg: Expand fallback sub2 " Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 108/163] tcg: Do not default add2/sub2_i32 for 32-bit hosts Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 109/163] tcg/mips: Drop support for add2/sub2 Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 110/163] tcg/riscv: " Richard Henderson
2025-04-15 22:05 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 111/163] tcg: Move i into each for loop in liveness_pass_1 Richard Henderson
2025-04-15 22:07 ` Pierrick Bouvier
2025-04-16 6:37 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 112/163] tcg: Sink def, nb_iargs, nb_oargs loads " Richard Henderson
2025-04-15 22:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 113/163] tcg: Add add/sub with carry opcodes and infrastructure Richard Henderson
2025-04-16 19:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 114/163] tcg: Add TCGOutOp structures for add/sub carry opcodes Richard Henderson
2025-04-16 18:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 115/163] tcg/optimize: Handle add/sub with " Richard Henderson
2025-04-16 19:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 116/163] tcg/optimize: With two const operands, prefer 0 in arg1 Richard Henderson
2025-04-16 19:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 117/163] tcg: Use add carry opcodes to expand add2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 118/163] tcg: Use sub carry opcodes to expand sub2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 119/163] tcg/i386: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 120/163] tcg/i386: Implement add/sub carry opcodes Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 121/163] tcg/i386: Remove support for add2/sub2 Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 122/163] tcg/i386: Special case addci r, 0, 0 Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 123/163] tcg: Add tcg_gen_addcio_{i32,i64,tl} Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-22 16:30 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 124/163] target/arm: Use tcg_gen_addcio_* for ADCS Richard Henderson
2025-04-16 19:00 ` Pierrick Bouvier
2025-04-22 16:15 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 125/163] target/hppa: Use tcg_gen_addcio_i64 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:17 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 126/163] target/microblaze: Use tcg_gen_addcio_i32 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:28 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 127/163] target/openrisc: Use tcg_gen_addcio_* for ADDC Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:32 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 128/163] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF Richard Henderson
2025-04-16 14:08 ` Nicholas Piggin
2025-04-16 19:08 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 129/163] target/s390x: Use tcg_gen_addcio_i64 for op_addc64 Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 130/163] target/sh4: Use tcg_gen_addcio_i32 for addc Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:34 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 131/163] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 132/163] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:38 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 133/163] tcg/aarch64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:10 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 134/163] tcg/aarch64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:13 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 135/163] tcg/arm: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 136/163] tcg/arm: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 137/163] tcg/ppc: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 138/163] tcg/ppc: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 139/163] tcg/s390x: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 140/163] tcg/s390: Add TCG_CT_CONST_N32 Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 141/163] tcg/s390x: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 142/163] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 143/163] tcg/s390x: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 144/163] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc Richard Henderson
2025-04-16 6:40 ` Philippe Mathieu-Daudé
2025-04-16 19:19 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 145/163] tcg/sparc64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 146/163] tcg/sparc64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 147/163] tcg/tci: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:36 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 148/163] tcg/tci: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 149/163] tcg: Remove add2/sub2 opcodes Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-22 16:42 ` Philippe Mathieu-Daudé
2025-04-22 17:10 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 150/163] tcg: Formalize tcg_out_mb Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-22 16:44 ` Philippe Mathieu-Daudé
2025-04-15 19:25 ` [PATCH v4 151/163] tcg: Formalize tcg_out_br Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 152/163] tcg: Formalize tcg_out_goto_ptr Richard Henderson
2025-04-16 20:45 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 153/163] tcg: Assign TCGOP_TYPE in liveness_pass_2 Richard Henderson
2025-04-16 20:46 ` Pierrick Bouvier
2025-04-18 10:46 ` Nicholas Piggin
2025-04-21 16:28 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 154/163] tcg: Convert ld to TCGOutOpLoad Richard Henderson
2025-04-16 20:52 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 155/163] tcg: Merge INDEX_op_ld*_{i32,i64} Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 156/163] tcg: Convert st to TCGOutOpStore Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 157/163] tcg: Merge INDEX_op_st*_{i32,i64} Richard Henderson
2025-04-16 7:05 ` Philippe Mathieu-Daudé
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 158/163] tcg: Stash MemOp size in TCGOP_FLAGS Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 20:54 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_* Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 19:24 ` Richard Henderson
2025-04-16 20:55 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 160/163] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} Richard Henderson
2025-04-16 20:56 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 161/163] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} Richard Henderson
2025-04-16 20:57 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 162/163] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} Richard Henderson
2025-04-16 20:58 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 163/163] tcg: Remove tcg_out_op Richard Henderson
2025-04-16 19:04 ` Pierrick Bouvier
2025-04-16 13:24 ` [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Nicholas Piggin
2025-04-16 23:38 ` Pierrick Bouvier
2025-04-17 0:18 ` Richard Henderson
2025-04-17 0:49 ` Pierrick Bouvier
2025-04-17 12:02 ` BALATON Zoltan
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