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([2602:47:d490:6901:a7b4:380e:e513:5ef2]) by smtp.gmail.com with ESMTPSA id l7-20020a17090a150700b002636dfcc6f5sm5341979pja.3.2023.07.30.10.50.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Jul 2023 10:50:52 -0700 (PDT) Message-ID: <8dcbe033-bf15-4df3-5042-5fbd3319ad22@linaro.org> Date: Sun, 30 Jul 2023 10:50:50 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH] target/hppa: Move iaoq registers and thus reduce generated code size Content-Language: en-US To: Helge Deller , Laurent Vivier , qemu-devel@nongnu.org References: From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.101, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/30/23 09:30, Helge Deller wrote: > On hppa the Instruction Address Offset Queue (IAOQ) registers specifies > the next to-be-executed instructions addresses. Each generated TB writes those > registers at least once, so those registers are used heavily in generated > code. > > Looking at the generated assembly, for a x86-64 host this code > to write the address $0x7ffe826f into iaoq_f is generated: > 0x7f73e8000184: c7 85 d4 01 00 00 6f 82 movl $0x7ffe826f, 0x1d4(%rbp) > 0x7f73e800018c: fe 7f > 0x7f73e800018e: c7 85 d8 01 00 00 73 82 movl $0x7ffe8273, 0x1d8(%rbp) > 0x7f73e8000196: fe 7f > > With the trivial change, by moving the variables iaoq_f and iaoq_b to > the top of struct CPUArchState, the offset to %rbp is reduced (from > 0x1d4 to 0), which allows the x86-64 tcg to generate 3 bytes less of > generated code per move instruction: > 0x7fc1e800018c: c7 45 00 6f 82 fe 7f movl $0x7ffe826f, (%rbp) > 0x7fc1e8000193: c7 45 04 73 82 fe 7f movl $0x7ffe8273, 4(%rbp) > > Overall this is a reduction of generated code (not a reduction of > number of instructions). > A test run with checks the generated code size by running "/bin/ls" > with qemu-user shows that the code size shrinks from 1616767 to 1569273 > bytes, which is ~97% of the former size. > > Signed-off-by: Helge Deller Reviewed-by: Richard Henderson r~