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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v4 52/57] tcg/i386: Honor 64-bit atomicity in 32-bit mode Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org References: <20230503070656.1746170-1-richard.henderson@linaro.org> <20230503070656.1746170-53-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.802, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/5/23 14:27, Peter Maydell wrote: > On Wed, 3 May 2023 at 08:18, Richard Henderson > wrote: >> >> Use the fpu to perform 64-bit loads and stores. >> >> Signed-off-by: Richard Henderson > > >> @@ -2091,7 +2095,20 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, >> datalo = datahi; >> datahi = t; >> } >> - if (h.base == datalo || h.index == datalo) { >> + if (h.atom == MO_64) { >> + /* >> + * Atomicity requires that we use use a single 8-byte load. >> + * For simplicity and code size, always use the FPU for this. >> + * Similar insns using SSE/AVX are merely larger. > > I'm surprised there's no performance penalty for throwing old-school > FPU insns into what is presumably otherwise code that's only > using modern SSE. I have no idea about performance. We don't require SSE for TCG at the moment. > I assume the caller has arranged that the top of the stack > is trashable at this point? The entire fpu stack is call-clobbered. r~