[PATCH 0/4] Clean up end-of-instruction processing

[PATCH 0/4] Clean up end-of-instruction processing

[Taylor Simpson]

The changes to packet processing have made some of the end-of-instruction
processing obsolete.  With the addition of gen_analyze_funcs.py and the
ability to short-circuit a packet commit, we no longer need to "log" the
register writes of each instruction.

Taylor Simpson (4):
  Hexagon (target/hexagon) Remove gen_log_reg_write
  Hexagon (target/hexagon) s/gen_log_pred_write/gen_pred_write
  Hexagon (target/hexagon) s/gen_log_vreg_write/gen_vreg_write
  Hexagon (target/hexagon) s/log_write/gen_write

 target/hexagon/gen_tcg.h                    | 11 ++-
 target/hexagon/genptr.h                     |  3 +-
 target/hexagon/genptr.c                     | 86 +++++++++------------
 target/hexagon/idef-parser/parser-helpers.c |  4 +-
 target/hexagon/README                       | 10 ++-
 target/hexagon/gen_tcg_funcs.py             |  3 +-
 target/hexagon/hex_common.py                | 56 +++++++-------
 7 files changed, 77 insertions(+), 96 deletions(-)

-- 
2.43.0

[PATCH 1/4] Hexagon (target/hexagon) Remove gen_log_reg_write

[Taylor Simpson]

The gen_log_reg_write function is a memnant of the original Hexagon
target design.  With the addition of gen_analyze_funcs.py and the
ability to short-circuit a packet commit, this function can be
removed.

Note that the implementation of gen_log_reg_write contains a check
of the register mutability mask.  This is only needed for control
registers, so we move it to gen_write_ctrl_reg.

We do need the gen_log_reg_write_pair function, but the name is
now misleading, so we change the name go gen_write_reg_pair.

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/gen_tcg.h                    |  7 +--
 target/hexagon/genptr.h                     |  1 -
 target/hexagon/genptr.c                     | 64 ++++++++-------------
 target/hexagon/idef-parser/parser-helpers.c |  2 +-
 target/hexagon/README                       | 10 ++--
 target/hexagon/gen_tcg_funcs.py             |  1 -
 target/hexagon/hex_common.py                | 14 ++---
 7 files changed, 40 insertions(+), 59 deletions(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 8a3b801287..10123336b1 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -509,10 +509,9 @@
 /* sub-instruction version (no RxV, so handle it manually) */
 #define fGEN_TCG_SS2_allocframe(SHORTCODE) \
     do { \
-        TCGv r29 = tcg_temp_new(); \
+        TCGv r29 = get_result_gpr(ctx, HEX_REG_SP); \
         tcg_gen_mov_tl(r29, hex_gpr[HEX_REG_SP]); \
         gen_allocframe(ctx, r29, uiV); \
-        gen_log_reg_write(ctx, HEX_REG_SP, r29); \
     } while (0)
 
 /*
@@ -528,7 +527,7 @@
     do { \
         TCGv_i64 r31_30 = tcg_temp_new_i64(); \
         gen_deallocframe(ctx, r31_30, hex_gpr[HEX_REG_FP]); \
-        gen_log_reg_write_pair(ctx, HEX_REG_FP, r31_30); \
+        gen_write_reg_pair(ctx, HEX_REG_FP, r31_30); \
     } while (0)
 
 /*
@@ -546,7 +545,7 @@
     do { \
         TCGv_i64 RddV = get_result_gpr_pair(ctx, HEX_REG_FP); \
         gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \
-        gen_log_reg_write_pair(ctx, HEX_REG_FP, RddV); \
+        gen_write_reg_pair(ctx, HEX_REG_FP, RddV); \
     } while (0)
 
 /*
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index a4b43c2910..d932255042 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -37,7 +37,6 @@ TCGv gen_read_reg(TCGv result, int num);
 TCGv gen_read_preg(TCGv pred, uint8_t num);
 TCGv get_result_gpr(DisasContext *ctx, int rnum);
 TCGv get_result_pred(DisasContext *ctx, int pnum);
-void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val);
 void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
 void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
 void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index cecaece4ae..e58021ed6c 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -94,25 +94,17 @@ static TCGv_i64 get_result_gpr_pair(DisasContext *ctx, int rnum)
     return result;
 }
 
-void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val)
-{
-    const target_ulong reg_mask = reg_immut_masks[rnum];
-
-    gen_masked_reg_write(val, hex_gpr[rnum], reg_mask);
-    tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val);
-}
-
-static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 val)
+static void gen_write_reg_pair(DisasContext *ctx, int rnum, TCGv_i64 val)
 {
     TCGv val32 = tcg_temp_new();
 
     /* Low word */
     tcg_gen_extrl_i64_i32(val32, val);
-    gen_log_reg_write(ctx, rnum, val32);
+    tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val32);
 
     /* High word */
     tcg_gen_extrh_i64_i32(val32, val);
-    gen_log_reg_write(ctx, rnum + 1, val32);
+    tcg_gen_mov_tl(get_result_gpr(ctx, rnum + 1), val32);
 }
 
 TCGv get_result_pred(DisasContext *ctx, int pnum)
@@ -240,7 +232,9 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
     if (reg_num == HEX_REG_P3_0_ALIASED) {
         gen_write_p3_0(ctx, val);
     } else {
-        gen_log_reg_write(ctx, reg_num, val);
+        const target_ulong reg_mask = reg_immut_masks[reg_num];
+        gen_masked_reg_write(val, hex_gpr[reg_num], reg_mask);
+        tcg_gen_mov_tl(get_result_gpr(ctx, reg_num), val);
         if (reg_num == HEX_REG_QEMU_PKT_CNT) {
             ctx->num_packets = 0;
         }
@@ -256,23 +250,15 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
 static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
                                            TCGv_i64 val)
 {
-    if (reg_num == HEX_REG_P3_0_ALIASED) {
-        TCGv result = get_result_gpr(ctx, reg_num + 1);
-        TCGv val32 = tcg_temp_new();
-        tcg_gen_extrl_i64_i32(val32, val);
-        gen_write_p3_0(ctx, val32);
-        tcg_gen_extrh_i64_i32(val32, val);
-        tcg_gen_mov_tl(result, val32);
-    } else {
-        gen_log_reg_write_pair(ctx, reg_num, val);
-        if (reg_num == HEX_REG_QEMU_PKT_CNT) {
-            ctx->num_packets = 0;
-            ctx->num_insns = 0;
-        }
-        if (reg_num == HEX_REG_QEMU_HVX_CNT) {
-            ctx->num_hvx_insns = 0;
-        }
-    }
+    TCGv val32 = tcg_temp_new();
+
+    /* Low word */
+    tcg_gen_extrl_i64_i32(val32, val);
+    gen_write_ctrl_reg(ctx, reg_num, val32);
+
+    /* High word */
+    tcg_gen_extrh_i64_i32(val32, val);
+    gen_write_ctrl_reg(ctx, reg_num + 1, val32);
 }
 
 TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
@@ -541,8 +527,8 @@ static inline void gen_loop0r(DisasContext *ctx, TCGv RsV, int riV)
 {
     fIMMEXT(riV);
     fPCALIGN(riV);
-    gen_log_reg_write(ctx, HEX_REG_LC0, RsV);
-    gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->pkt->pc + riV));
+    tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);
+    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV);
     gen_set_usr_fieldi(ctx, USR_LPCFG, 0);
 }
 
@@ -555,8 +541,8 @@ static inline void gen_loop1r(DisasContext *ctx, TCGv RsV, int riV)
 {
     fIMMEXT(riV);
     fPCALIGN(riV);
-    gen_log_reg_write(ctx, HEX_REG_LC1, RsV);
-    gen_log_reg_write(ctx, HEX_REG_SA1, tcg_constant_tl(ctx->pkt->pc + riV));
+    tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC1), RsV);
+    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA1), ctx->pkt->pc + riV);
 }
 
 static void gen_loop1i(DisasContext *ctx, int count, int riV)
@@ -568,8 +554,8 @@ static void gen_ploopNsr(DisasContext *ctx, int N, TCGv RsV, int riV)
 {
     fIMMEXT(riV);
     fPCALIGN(riV);
-    gen_log_reg_write(ctx, HEX_REG_LC0, RsV);
-    gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->pkt->pc + riV));
+    tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);
+    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV);
     gen_set_usr_fieldi(ctx, USR_LPCFG, N);
     gen_log_pred_write(ctx, 3, tcg_constant_tl(0));
 }
@@ -773,25 +759,23 @@ static void gen_framecheck(TCGv EA, int framesize)
 
 static void gen_allocframe(DisasContext *ctx, TCGv r29, int framesize)
 {
-    TCGv r30 = tcg_temp_new();
+    TCGv r30 = get_result_gpr(ctx, HEX_REG_FP);
     TCGv_i64 frame;
     tcg_gen_addi_tl(r30, r29, -8);
     frame = gen_frame_scramble();
     gen_store8(tcg_env, r30, frame, ctx->insn->slot);
-    gen_log_reg_write(ctx, HEX_REG_FP, r30);
     gen_framecheck(r30, framesize);
     tcg_gen_subi_tl(r29, r30, framesize);
 }
 
 static void gen_deallocframe(DisasContext *ctx, TCGv_i64 r31_30, TCGv r30)
 {
-    TCGv r29 = tcg_temp_new();
+    TCGv r29 = get_result_gpr(ctx, HEX_REG_SP);
     TCGv_i64 frame = tcg_temp_new_i64();
     gen_load_frame(ctx, frame, r30);
     gen_frame_unscramble(frame);
     tcg_gen_mov_i64(r31_30, frame);
     tcg_gen_addi_tl(r29, r30, 8);
-    gen_log_reg_write(ctx, HEX_REG_SP, r29);
 }
 #endif
 
@@ -833,7 +817,7 @@ static void gen_cond_return_subinsn(DisasContext *ctx, TCGCond cond, TCGv pred)
 {
     TCGv_i64 RddV = get_result_gpr_pair(ctx, HEX_REG_FP);
     gen_cond_return(ctx, RddV, hex_gpr[HEX_REG_FP], pred, cond);
-    gen_log_reg_write_pair(ctx, HEX_REG_FP, RddV);
+    gen_write_reg_pair(ctx, HEX_REG_FP, RddV);
 }
 
 static void gen_endloop0(DisasContext *ctx)
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
index 1dc52b4e02..f5802ceadb 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1315,7 +1315,7 @@ void gen_write_reg(Context *c, YYLTYPE *locp, HexValue *reg, HexValue *value)
     value_m = rvalue_materialize(c, locp, &value_m);
     OUT(c,
         locp,
-        "gen_log_reg_write(ctx, ", &reg->reg.id, ", ",
+        "tcg_gen_mov_tl(get_result_gpr(ctx, ", &reg->reg.id, "), ",
         &value_m, ");\n");
 }
 
diff --git a/target/hexagon/README b/target/hexagon/README
index ca617e3364..1938c91af8 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -80,12 +80,14 @@ tcg_funcs_generated.c.inc
                     Insn *insn,
                     Packet *pkt)
     {
-        TCGv RdV = tcg_temp_new();
+        Insn *insn G_GNUC_UNUSED = ctx->insn;
         const int RdN = insn->regno[0];
-        TCGv RsV = hex_gpr[insn->regno[1]];
-        TCGv RtV = hex_gpr[insn->regno[2]];
+        TCGv RdV = get_result_gpr(ctx, RdN);
+        const int RsN = insn->regno[1];
+        TCGv RsV = hex_gpr[RsN];
+        const int RtN = insn->regno[2];
+        TCGv RtV = hex_gpr[RtN];
         gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
-        gen_log_reg_write(ctx, RdN, RdV);
     }
 
 helper_funcs_generated.c.inc
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index c2ba91ddc0..bd241afde1 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -35,7 +35,6 @@
 ##        TCGv RsV = hex_gpr[insn->regno[1]];
 ##        TCGv RtV = hex_gpr[insn->regno[2]];
 ##        <GEN>
-##        gen_log_reg_write(ctx, RdN, RdV);
 ##    }
 ##
 ##       where <GEN> depends on hex_common.skip_qemu_helper(tag)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 6803908718..093def9386 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -452,9 +452,8 @@ def decl_tcg(self, f, tag, regno):
             TCGv {self.reg_tcg()} = get_result_gpr(ctx, {self.reg_num});
         """))
     def log_write(self, f, tag):
-        f.write(code_fmt(f"""\
-            gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()});
-        """))
+        ## No write needed
+        return
     def analyze_write(self, f, tag, regno):
         predicated = "true" if is_predicated(tag) else "false"
         f.write(code_fmt(f"""\
@@ -496,9 +495,8 @@ def decl_tcg(self, f, tag, regno):
                 tcg_gen_mov_tl({self.reg_tcg()}, hex_gpr[{self.reg_num}]);
             """))
     def log_write(self, f, tag):
-        f.write(code_fmt(f"""\
-            gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()});
-        """))
+        ## No write needed
+        return
     def analyze_read(self, f, regno):
         f.write(code_fmt(f"""\
             ctx_log_reg_read(ctx, {self.reg_num});
@@ -630,7 +628,7 @@ def decl_tcg(self, f, tag, regno):
         """))
     def log_write(self, f, tag):
         f.write(code_fmt(f"""\
-            gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
+            gen_write_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
     def analyze_write(self, f, tag, regno):
         predicated = "true" if is_predicated(tag) else "false"
@@ -664,7 +662,7 @@ def decl_tcg(self, f, tag, regno):
         """))
     def log_write(self, f, tag):
         f.write(code_fmt(f"""\
-            gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
+            gen_write_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
     def analyze_read(self, f, regno):
         f.write(code_fmt(f"""\
-- 
2.43.0

[PATCH 2/4] Hexagon (target/hexagon) s/gen_log_pred_write/gen_pred_write

[Taylor Simpson]

The function doesn't "log" anything, it just generates the write

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/gen_tcg.h                    |  4 ++--
 target/hexagon/genptr.h                     |  2 +-
 target/hexagon/genptr.c                     | 14 +++++++-------
 target/hexagon/idef-parser/parser-helpers.c |  2 +-
 target/hexagon/hex_common.py                |  4 ++--
 5 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 10123336b1..60f3d295da 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -599,7 +599,7 @@
         TCGv p0 = tcg_temp_new(); \
         gen_helper_cabacdecbin_pred(p0, RssV, RttV); \
         gen_helper_cabacdecbin_val(RddV, RssV, RttV); \
-        gen_log_pred_write(ctx, 0, p0); \
+        gen_pred_write(ctx, 0, p0); \
     } while (0)
 
 /*
@@ -914,7 +914,7 @@
     do { \
         TCGv p0 = tcg_temp_new(); \
         gen_comparei(TCG_COND_EQ, p0, RsV, uiV); \
-        gen_log_pred_write(ctx, 0, p0); \
+        gen_pred_write(ctx, 0, p0); \
     } while (0)
 
 #define fGEN_TCG_J2_jump(SHORTCODE) \
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index d932255042..228d7f1d7d 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -37,7 +37,7 @@ TCGv gen_read_reg(TCGv result, int num);
 TCGv gen_read_preg(TCGv pred, uint8_t num);
 TCGv get_result_gpr(DisasContext *ctx, int rnum);
 TCGv get_result_pred(DisasContext *ctx, int pnum);
-void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
+void gen_pred_write(DisasContext *ctx, int pnum, TCGv val);
 void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
 void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
 void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val);
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index e58021ed6c..bfbbd61c33 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -120,7 +120,7 @@ TCGv get_result_pred(DisasContext *ctx, int pnum)
     }
 }
 
-void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
+void gen_pred_write(DisasContext *ctx, int pnum, TCGv val)
 {
     TCGv pred = get_result_pred(ctx, pnum);
     TCGv base_val = tcg_temp_new();
@@ -215,7 +215,7 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv control_reg)
     TCGv hex_p8 = tcg_temp_new();
     for (int i = 0; i < NUM_PREGS; i++) {
         tcg_gen_extract_tl(hex_p8, control_reg, i * 8, 8);
-        gen_log_pred_write(ctx, i, hex_p8);
+        gen_pred_write(ctx, i, hex_p8);
     }
 }
 
@@ -557,7 +557,7 @@ static void gen_ploopNsr(DisasContext *ctx, int N, TCGv RsV, int riV)
     tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);
     tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV);
     gen_set_usr_fieldi(ctx, USR_LPCFG, N);
-    gen_log_pred_write(ctx, 3, tcg_constant_tl(0));
+    gen_pred_write(ctx, 3, tcg_constant_tl(0));
 }
 
 static void gen_ploopNsi(DisasContext *ctx, int N, int count, int riV)
@@ -597,7 +597,7 @@ static void gen_cmpnd_cmp_jmp(DisasContext *ctx,
     if (ctx->insn->part1) {
         TCGv pred = tcg_temp_new();
         gen_compare(cond1, pred, arg1, arg2);
-        gen_log_pred_write(ctx, pnum, pred);
+        gen_pred_write(ctx, pnum, pred);
     } else {
         TCGv pred = tcg_temp_new();
         tcg_gen_mov_tl(pred, ctx->new_pred_value[pnum]);
@@ -654,7 +654,7 @@ static void gen_cmpnd_tstbit0_jmp(DisasContext *ctx,
         TCGv pred = tcg_temp_new();
         tcg_gen_andi_tl(pred, arg, 1);
         gen_8bitsof(pred, pred);
-        gen_log_pred_write(ctx, pnum, pred);
+        gen_pred_write(ctx, pnum, pred);
     } else {
         TCGv pred = tcg_temp_new();
         tcg_gen_mov_tl(pred, ctx->new_pred_value[pnum]);
@@ -834,7 +834,7 @@ static void gen_endloop0(DisasContext *ctx)
     TCGLabel *label1 = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1);
     {
-        gen_log_pred_write(ctx, 3, tcg_constant_tl(0xff));
+        gen_pred_write(ctx, 3, tcg_constant_tl(0xff));
     }
     gen_set_label(label1);
 
@@ -908,7 +908,7 @@ static void gen_endloop01(DisasContext *ctx)
      */
     tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1);
     {
-        gen_log_pred_write(ctx, 3, tcg_constant_tl(0xff));
+        gen_pred_write(ctx, 3, tcg_constant_tl(0xff));
     }
     gen_set_label(label1);
 
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
index f5802ceadb..70bfa64432 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1713,7 +1713,7 @@ void gen_pred_assign(Context *c, YYLTYPE *locp, HexValue *left_pred,
     /* Extract first 8 bits, and store new predicate value */
     OUT(c, locp, "tcg_gen_andi_i32(", left_pred, ", ", &r, ", 0xff);\n");
     if (is_direct) {
-        OUT(c, locp, "gen_log_pred_write(ctx, ", pred_id, ", ", left_pred,
+        OUT(c, locp, "gen_pred_write(ctx, ", pred_id, ", ", left_pred,
             ");\n");
     }
 }
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 093def9386..1277fec9a2 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -571,7 +571,7 @@ def decl_tcg(self, f, tag, regno):
         """))
     def log_write(self, f, tag):
         f.write(code_fmt(f"""\
-            gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
+            gen_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
     def analyze_write(self, f, tag, regno):
         f.write(code_fmt(f"""\
@@ -608,7 +608,7 @@ def decl_tcg(self, f, tag, regno):
         """))
     def log_write(self, f, tag):
         f.write(code_fmt(f"""\
-            gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
+            gen_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
     def analyze_read(self, f, regno):
         f.write(code_fmt(f"""\
-- 
2.43.0

[PATCH 3/4] Hexagon (target/hexagon) s/gen_log_vreg_write/gen_vreg_write

[Taylor Simpson]

Note there are two functions impacted
    gen_log_vreg_write          -> gen_vreg_write
    gen_log_vreg_write_pair     -> gen_vreg_write_pair
These functions don't "log" anything, they just generate the write

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/genptr.c      | 8 ++++----
 target/hexagon/hex_common.py | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index bfbbd61c33..616db17907 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -1174,7 +1174,7 @@ static intptr_t vreg_src_off(DisasContext *ctx, int num)
     return offset;
 }
 
-static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num,
+static void gen_vreg_write(DisasContext *ctx, intptr_t srcoff, int num,
                                VRegWriteType type)
 {
     intptr_t dstoff;
@@ -1190,12 +1190,12 @@ static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num,
     }
 }
 
-static void gen_log_vreg_write_pair(DisasContext *ctx, intptr_t srcoff, int num,
+static void gen_vreg_write_pair(DisasContext *ctx, intptr_t srcoff, int num,
                                     VRegWriteType type)
 {
-    gen_log_vreg_write(ctx, srcoff, num ^ 0, type);
+    gen_vreg_write(ctx, srcoff, num ^ 0, type);
     srcoff += sizeof(MMVector);
-    gen_log_vreg_write(ctx, srcoff, num ^ 1, type);
+    gen_vreg_write(ctx, srcoff, num ^ 1, type);
 }
 
 static intptr_t get_result_qreg(DisasContext *ctx, int qnum)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 1277fec9a2..6b683487bc 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -823,8 +823,8 @@ def decl_tcg(self, f, tag, regno):
             """))
     def log_write(self, f, tag):
         f.write(code_fmt(f"""\
-            gen_log_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},
-                               {hvx_newv(tag)});
+            gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},
+                           {hvx_newv(tag)});
         """))
     def helper_hvx_desc(self, f):
         f.write(code_fmt(f"""\
@@ -915,8 +915,8 @@ def decl_tcg(self, f, tag, regno):
             """))
     def log_write(self, f, tag):
         f.write(code_fmt(f"""\
-            gen_log_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},
-                                    {hvx_newv(tag)});
+            gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},
+                                {hvx_newv(tag)});
         """))
     def helper_hvx_desc(self, f):
         f.write(code_fmt(f"""\
-- 
2.43.0

[PATCH 4/4] Hexagon (target/hexagon) s/log_write/gen_write

[Taylor Simpson]

These functions don't "log" anything, they just generate the write

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/gen_tcg_funcs.py |  2 +-
 target/hexagon/hex_common.py    | 30 +++++++++++++++---------------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index bd241afde1..3e531bd540 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -94,7 +94,7 @@ def gen_tcg_func(f, tag, regs, imms):
     for regtype, regid in regs:
         reg = hex_common.get_register(tag, regtype, regid)
         if reg.is_written():
-            reg.log_write(f, tag)
+            reg.gen_write(f, tag)
 
     f.write("}\n\n")
 
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 6b683487bc..c0e9f26aeb 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -451,7 +451,7 @@ def decl_tcg(self, f, tag, regno):
         f.write(code_fmt(f"""\
             TCGv {self.reg_tcg()} = get_result_gpr(ctx, {self.reg_num});
         """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         ## No write needed
         return
     def analyze_write(self, f, tag, regno):
@@ -494,7 +494,7 @@ def decl_tcg(self, f, tag, regno):
             f.write(code_fmt(f"""\
                 tcg_gen_mov_tl({self.reg_tcg()}, hex_gpr[{self.reg_num}]);
             """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         ## No write needed
         return
     def analyze_read(self, f, regno):
@@ -517,7 +517,7 @@ def decl_tcg(self, f, tag, regno):
         f.write(code_fmt(f"""\
             TCGv {self.reg_tcg()} = get_result_gpr(ctx, {self.reg_num});
         """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         f.write(code_fmt(f"""\
             gen_write_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
@@ -569,7 +569,7 @@ def decl_tcg(self, f, tag, regno):
         f.write(code_fmt(f"""\
             TCGv {self.reg_tcg()} = tcg_temp_new();
         """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         f.write(code_fmt(f"""\
             gen_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
@@ -606,7 +606,7 @@ def decl_tcg(self, f, tag, regno):
             TCGv {self.reg_tcg()} = tcg_temp_new();
             tcg_gen_mov_tl({self.reg_tcg()}, hex_pred[{self.reg_num}]);
         """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         f.write(code_fmt(f"""\
             gen_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
@@ -626,7 +626,7 @@ def decl_tcg(self, f, tag, regno):
             TCGv_i64 {self.reg_tcg()} =
                 get_result_gpr_pair(ctx, {self.reg_num});
         """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         f.write(code_fmt(f"""\
             gen_write_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
@@ -660,7 +660,7 @@ def decl_tcg(self, f, tag, regno):
                                    hex_gpr[{self.reg_num}],
                                    hex_gpr[{self.reg_num} + 1]);
         """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         f.write(code_fmt(f"""\
             gen_write_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
@@ -685,7 +685,7 @@ def decl_tcg(self, f, tag, regno):
             TCGv_i64 {self.reg_tcg()} =
                 get_result_gpr_pair(ctx, {self.reg_num});
         """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         f.write(code_fmt(f"""\
             gen_write_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
         """))
@@ -723,7 +723,7 @@ def decl_tcg(self, f, tag, regno):
                 TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
                 tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
             """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         pass
     def helper_hvx_desc(self, f):
         f.write(code_fmt(f"""\
@@ -789,7 +789,7 @@ def decl_tcg(self, f, tag, regno):
                 TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
                 tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
             """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         pass
     def helper_hvx_desc(self, f):
         f.write(code_fmt(f"""\
@@ -821,7 +821,7 @@ def decl_tcg(self, f, tag, regno):
                                  vreg_src_off(ctx, {self.reg_num}),
                                  sizeof(MMVector), sizeof(MMVector));
             """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         f.write(code_fmt(f"""\
             gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},
                            {hvx_newv(tag)});
@@ -854,7 +854,7 @@ def decl_tcg(self, f, tag, regno):
                 TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
                 tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
             """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         pass
     def helper_hvx_desc(self, f):
         f.write(code_fmt(f"""\
@@ -913,7 +913,7 @@ def decl_tcg(self, f, tag, regno):
                 TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
                 tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
             """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         f.write(code_fmt(f"""\
             gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},
                                 {hvx_newv(tag)});
@@ -946,7 +946,7 @@ def decl_tcg(self, f, tag, regno):
                 TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
                 tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
             """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         pass
     def helper_hvx_desc(self, f):
         f.write(code_fmt(f"""\
@@ -993,7 +993,7 @@ def decl_tcg(self, f, tag, regno):
                 TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
                 tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
             """))
-    def log_write(self, f, tag):
+    def gen_write(self, f, tag):
         pass
     def helper_hvx_desc(self, f):
         f.write(code_fmt(f"""\
-- 
2.43.0

Re: [PATCH 0/4] Clean up end-of-instruction processing

[Philippe Mathieu-Daudé]

Hi Taylor,

On 15/11/25 00:00, Taylor Simpson wrote:
> The changes to packet processing have made some of the end-of-instruction
> processing obsolete.  With the addition of gen_analyze_funcs.py and the
> ability to short-circuit a packet commit, we no longer need to "log" the
> register writes of each instruction.
> 
> Taylor Simpson (4):
>    Hexagon (target/hexagon) Remove gen_log_reg_write
>    Hexagon (target/hexagon) s/gen_log_pred_write/gen_pred_write
>    Hexagon (target/hexagon) s/gen_log_vreg_write/gen_vreg_write
>    Hexagon (target/hexagon) s/log_write/gen_write

I fail to apply your series, what is the base commit?

Thanks,

Phil.

Re: [PATCH 0/4] Clean up end-of-instruction processing

[Brian Cain]

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Maybe they're based on the other commits on my tree which are queued for
inclusion after 10.2?
https://github.com/quic/qemu/commits/hex-next-express/

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Re: [PATCH 0/4] Clean up end-of-instruction processing

[Philippe Mathieu-Daudé]

On 17/11/25 18:08, Brian Cain wrote:
> Maybe they're based on the other commits on my tree which are queued for 
> inclusion after 10.2? https://github.com/quic/qemu/commits/hex-next- 
> express/ <https://github.com/quic/qemu/commits/hex-next-express/>

Ah yes indeed, thank you Brian :)

Re: [PATCH 2/4] Hexagon (target/hexagon) s/gen_log_pred_write/gen_pred_write

[Philippe Mathieu-Daudé]

On 15/11/25 00:00, Taylor Simpson wrote:
> The function doesn't "log" anything, it just generates the write
> 
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>   target/hexagon/gen_tcg.h                    |  4 ++--
>   target/hexagon/genptr.h                     |  2 +-
>   target/hexagon/genptr.c                     | 14 +++++++-------
>   target/hexagon/idef-parser/parser-helpers.c |  2 +-
>   target/hexagon/hex_common.py                |  4 ++--
>   5 files changed, 13 insertions(+), 13 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH 3/4] Hexagon (target/hexagon) s/gen_log_vreg_write/gen_vreg_write

[Philippe Mathieu-Daudé]

On 15/11/25 00:00, Taylor Simpson wrote:
> Note there are two functions impacted
>      gen_log_vreg_write          -> gen_vreg_write
>      gen_log_vreg_write_pair     -> gen_vreg_write_pair
> These functions don't "log" anything, they just generate the write
> 
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>   target/hexagon/genptr.c      | 8 ++++----
>   target/hexagon/hex_common.py | 8 ++++----
>   2 files changed, 8 insertions(+), 8 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH 4/4] Hexagon (target/hexagon) s/log_write/gen_write

[Philippe Mathieu-Daudé]

On 15/11/25 00:00, Taylor Simpson wrote:
> These functions don't "log" anything, they just generate the write
> 
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>   target/hexagon/gen_tcg_funcs.py |  2 +-
>   target/hexagon/hex_common.py    | 30 +++++++++++++++---------------
>   2 files changed, 16 insertions(+), 16 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH 0/4] Clean up end-of-instruction processing

[Taylor Simpson]

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They are based on this one
commit bc831f37398b51dfe65d99a67bcff9352f84a9d2 (origin/staging,
origin/master, origin/HEAD)
Merge: 76929d6117 7dbe2d7df0
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Tue Oct 28 11:48:05 2025 +0100

They also apply cleanly to Brian's hex-next-express branch.

What error are you getting on your end?

Thanks,
Taylor


On Mon, Nov 17, 2025 at 10:08 AM Brian Cain <brian.cain@oss.qualcomm.com>
wrote:

> Maybe they're based on the other commits on my tree which are queued for
> inclusion after 10.2?
> https://github.com/quic/qemu/commits/hex-next-express/
>

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Re: [PATCH 0/4] Clean up end-of-instruction processing

[Taylor Simpson]

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FWIW, they also apply cleanly to this commit
commit e88510fcdc13380bd4895a17d6f8a0b3a3325b85 (HEAD -> master,
origin/staging, origin/master, origin/HEAD)
Merge: 409be85c2f 522444744e
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Fri Nov 14 17:59:05 2025 +0100

Taylor


On Mon, Nov 17, 2025 at 11:35 AM Taylor Simpson <ltaylorsimpson@gmail.com>
wrote:

>
> They are based on this one
> commit bc831f37398b51dfe65d99a67bcff9352f84a9d2 (origin/staging,
> origin/master, origin/HEAD)
> Merge: 76929d6117 7dbe2d7df0
> Author: Richard Henderson <richard.henderson@linaro.org>
> Date:   Tue Oct 28 11:48:05 2025 +0100
>
> They also apply cleanly to Brian's hex-next-express branch.
>
> What error are you getting on your end?
>
> Thanks,
> Taylor
>
>
> On Mon, Nov 17, 2025 at 10:08 AM Brian Cain <brian.cain@oss.qualcomm.com>
> wrote:
>
>> Maybe they're based on the other commits on my tree which are queued for
>> inclusion after 10.2?
>> https://github.com/quic/qemu/commits/hex-next-express/
>>
>

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