Re: [PATCH v8 1/2] target/riscv: Use tcg nodes for strided vector ld/st generation

[Richard Henderson <richard.henderson@linaro.org>]

On 9/13/25 02:17, Chao Liu wrote:
> +static void gen_check_vext_elem_mask(TCGLabel *label, TCGv_i64 mask, TCGv_i64 mask_offs)
> +{
> +    TCGv_i64 mask_offs_i64 = tcg_temp_new_i64();
> +    TCGv_ptr mask_offs_ptr = tcg_temp_new_ptr();
> +    TCGv_i64 mask_offs_rem = tcg_temp_new_i64();
> +    TCGv_i64 mask_elem = tcg_temp_new_i64();
> +
> +    tcg_gen_shri_tl(mask_offs_i64, mask_offs, 3);
> +    tcg_gen_add_tl(mask_offs_i64, mask_offs_i64, mask);
> +    tcg_gen_trunc_i64_ptr(mask_offs_ptr, mask_offs_i64);
> +    tcg_gen_ld_i64(mask_elem, mask_offs_ptr, 0);

You can remove the "mask" argument, simplifying the code here.

	tcg_gen_trunc_i64_ptr(ptr, mask_offs_i64);
	tcg_gen_add_ptr(ptr, ptr, tcg_env);
	tcg_gen_ld_i64(mask_elem, ptr, vreg_ofs(s, 0))

You can also change mask_offs to TCGv_i32, which replaces

	tcg_gen_extu_i32_ptr(pr, mask_offs_i32);

which more obviously does not discard data from mask_offs.


> +    tcg_gen_andi_tl(mask_offs_rem, mask_offs, 7);
> +    tcg_gen_shr_tl(mask_elem, mask_elem, mask_offs_rem);

The mask of 7 suggests you're only interested in the low 8 bits.  Which means either the 
load is wrong (we don't need to be loading 64 bits), or the mask and shift are wrong.


> +    tcg_gen_andi_tl(mask_elem, mask_elem, 1);
> +    tcg_gen_brcond_i64(TCG_COND_TSTNE, mask_elem, tcg_constant_i64(1), label);

The andi before the brcond is redundant with the TSTNE.


r~