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Mon, 15 Sep 2025 06:53:43 -0700 (PDT) Received: from [192.168.0.4] ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-25c3b0219f9sm130533695ad.123.2025.09.15.06.53.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Sep 2025 06:53:43 -0700 (PDT) Message-ID: <8e43c44f-609c-4a30-8559-a5dcb567b950@linaro.org> Date: Mon, 15 Sep 2025 06:53:41 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 1/2] target/riscv: Use tcg nodes for strided vector ld/st generation To: Chao Liu , paolo.savini@embecosm.com, npiggin@gmail.com, ebiggers@kernel.org, dbarboza@ventanamicro.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org References: <1f22506f44570abf3bb17bf144d398807be0ab40.1757690407.git.chao.liu@zevorn.cn> From: Richard Henderson Content-Language: en-US In-Reply-To: <1f22506f44570abf3bb17bf144d398807be0ab40.1757690407.git.chao.liu@zevorn.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/13/25 02:17, Chao Liu wrote: > +static void gen_check_vext_elem_mask(TCGLabel *label, TCGv_i64 mask, TCGv_i64 mask_offs) > +{ > + TCGv_i64 mask_offs_i64 = tcg_temp_new_i64(); > + TCGv_ptr mask_offs_ptr = tcg_temp_new_ptr(); > + TCGv_i64 mask_offs_rem = tcg_temp_new_i64(); > + TCGv_i64 mask_elem = tcg_temp_new_i64(); > + > + tcg_gen_shri_tl(mask_offs_i64, mask_offs, 3); > + tcg_gen_add_tl(mask_offs_i64, mask_offs_i64, mask); > + tcg_gen_trunc_i64_ptr(mask_offs_ptr, mask_offs_i64); > + tcg_gen_ld_i64(mask_elem, mask_offs_ptr, 0); You can remove the "mask" argument, simplifying the code here. tcg_gen_trunc_i64_ptr(ptr, mask_offs_i64); tcg_gen_add_ptr(ptr, ptr, tcg_env); tcg_gen_ld_i64(mask_elem, ptr, vreg_ofs(s, 0)) You can also change mask_offs to TCGv_i32, which replaces tcg_gen_extu_i32_ptr(pr, mask_offs_i32); which more obviously does not discard data from mask_offs. > + tcg_gen_andi_tl(mask_offs_rem, mask_offs, 7); > + tcg_gen_shr_tl(mask_elem, mask_elem, mask_offs_rem); The mask of 7 suggests you're only interested in the low 8 bits. Which means either the load is wrong (we don't need to be loading 64 bits), or the mask and shift are wrong. > + tcg_gen_andi_tl(mask_elem, mask_elem, 1); > + tcg_gen_brcond_i64(TCG_COND_TSTNE, mask_elem, tcg_constant_i64(1), label); The andi before the brcond is redundant with the TSTNE. r~