From: Richard Henderson <richard.henderson@linaro.org>
To: "Brenken, David (EFS-GH2)" <david.brenken@efs-auto.de>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
David Brenken <david.brenken@efs-auto.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "Biermanski, Lars \(EFS-GH3\)" <lars.biermanski@efs-auto.de>,
"Rasche, Robert \(EFS-GH2\)" <robert.rasche@efs-auto.de>,
"Hofstetter, Georg \(EFS-GH2\)" <Georg.Hofstetter@efs-auto.de>,
"Konopik, Andreas \(EFS-GH2\)" <andreas.konopik@efs-auto.de>
Subject: Re: [Qemu-devel] [PATCH 3/5] tricore: fix RRPW_INSERT instruction
Date: Fri, 7 Jun 2019 07:48:11 -0500 [thread overview]
Message-ID: <8e4f29db-fb2d-4053-2483-a2d92466ce35@linaro.org> (raw)
In-Reply-To: <34F764F04E859040BBA6C4FF41AB17D93B2DA4@AUDIINSX0410.audi.vwg>
On 6/6/19 2:26 AM, Brenken, David (EFS-GH2) wrote:
>>> case OPC2_32_RRPW_INSERT:
>>> - if (pos + width <= 31) {
>>> - tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
>>> - width, pos);
>> Can you explain the problem causing the bug? Deposit looks fine to me.
>> After reading the specs again, I agree that the check needs to be <= 32.
> The bug was recognized because of different behavior between actual hardware and QEMU.
> Just from looking at it I would say that deposit masks and then shifts the arg2 (D[b]) while the
> manual states to first shift D[b] and then mask it. I remember that it was a corner case (e.g.
> width + pos = 31 or 32).
The final two arguments to tcg_gen_deposit_tl are swapped.
It should be pos, width.
r~
next prev parent reply other threads:[~2019-06-07 12:58 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-05 6:11 [Qemu-devel] [PATCH 0/5] tricore: adding new instructions and fixing issues David Brenken
2019-06-05 6:11 ` [Qemu-devel] [PATCH 1/5] tricore: add FTOIZ instruction David Brenken
2019-06-05 14:27 ` Bastian Koppelmann
2019-06-05 6:11 ` [Qemu-devel] [PATCH 2/5] tricore: add UTOF instruction David Brenken
2019-06-05 14:34 ` Bastian Koppelmann
2019-06-05 6:11 ` [Qemu-devel] [PATCH 3/5] tricore: fix RRPW_INSERT instruction David Brenken
2019-06-05 14:34 ` Bastian Koppelmann
2019-06-06 7:26 ` Brenken, David (EFS-GH2)
2019-06-07 12:48 ` Richard Henderson [this message]
2019-06-12 5:48 ` Brenken, David (EFS-GH2)
2019-06-12 11:52 ` Bastian Koppelmann
2019-06-05 6:11 ` [Qemu-devel] [PATCH 4/5] tricore: add QSEED instruction David Brenken
2019-06-05 15:04 ` Bastian Koppelmann
2019-06-07 8:40 ` Konopik, Andreas (EFS-GH2)
2019-06-05 6:11 ` [Qemu-devel] [PATCH 5/5] tricore: reset DisasContext before generating code David Brenken
2019-06-05 9:01 ` Bastian Koppelmann
2019-06-06 11:44 ` Hofstetter, Georg (EFS-GH2)
2019-06-06 14:24 ` Bastian Koppelmann
2019-06-05 15:10 ` [Qemu-devel] [PATCH 0/5] tricore: adding new instructions and fixing issues Bastian Koppelmann
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