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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id d21sm709488oih.21.2019.06.07.05.48.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Jun 2019 05:48:15 -0700 (PDT) To: "Brenken, David (EFS-GH2)" , Bastian Koppelmann , David Brenken , "qemu-devel@nongnu.org" References: <20190605061126.10244-1-david.brenken@efs-auto.org> <20190605061126.10244-4-david.brenken@efs-auto.org> <34F764F04E859040BBA6C4FF41AB17D93B2DA4@AUDIINSX0410.audi.vwg> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <8e4f29db-fb2d-4053-2483-a2d92466ce35@linaro.org> Date: Fri, 7 Jun 2019 07:48:11 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <34F764F04E859040BBA6C4FF41AB17D93B2DA4@AUDIINSX0410.audi.vwg> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::329 Subject: Re: [Qemu-devel] [PATCH 3/5] tricore: fix RRPW_INSERT instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Biermanski, Lars \(EFS-GH3\)" , "Rasche, Robert \(EFS-GH2\)" , "Hofstetter, Georg \(EFS-GH2\)" , "Konopik, Andreas \(EFS-GH2\)" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/6/19 2:26 AM, Brenken, David (EFS-GH2) wrote: >>> case OPC2_32_RRPW_INSERT: >>> - if (pos + width <= 31) { >>> - tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], >>> - width, pos); >> Can you explain the problem causing the bug? Deposit looks fine to me. >> After reading the specs again, I agree that the check needs to be <= 32. > The bug was recognized because of different behavior between actual hardware and QEMU. > Just from looking at it I would say that deposit masks and then shifts the arg2 (D[b]) while the > manual states to first shift D[b] and then mask it. I remember that it was a corner case (e.g. > width + pos = 31 or 32). The final two arguments to tcg_gen_deposit_tl are swapped. It should be pos, width. r~