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Fri, 17 Oct 2025 11:47:50 -0700 (PDT) Received: from [192.168.0.4] ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7a22ff38d30sm287894b3a.29.2025.10.17.11.47.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Oct 2025 11:47:50 -0700 (PDT) Message-ID: <8f0db5c1-f20b-4b7a-8d6c-76ce7ec7b4e0@linaro.org> Date: Fri, 17 Oct 2025 11:47:48 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] target-info: Introduce runtime TARGET_PHYS_ADDR_SPACE_BITS To: Anton Johansson , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Cc: Paolo Bonzini , pierrick.bouvier@linaro.org, qemu-devel@nongnu.org, alistair.francis@wdc.com, palmer@dabbelt.com, Song Gao , Helge Deller References: <20251015-feature-single-binary-hw-v1-v1-0-8b416eda42cf@rev.ng> <20251015-feature-single-binary-hw-v1-v1-4-8b416eda42cf@rev.ng> <673e3c7b-b8ef-4908-b74d-62203b131229@linaro.org> <7jzcbl2yqkssu5lshz4umayaesoxwg3gcskrrkobc37df2p4z2@s26yst4mfxoe> From: Richard Henderson Content-Language: en-US In-Reply-To: <7jzcbl2yqkssu5lshz4umayaesoxwg3gcskrrkobc37df2p4z2@s26yst4mfxoe> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/17/25 09:11, Anton Johansson wrote: > Hmm you're right looking at git grep -C1 TARGET_PHYS_ADDR_SPACE_BITS > (output below excluding the hw/riscv change in the following patch), > there are really aren't that many uses left and none in common code. > > We still got to move it to a runtime value somewhere though, what > would be a more suitable location? Maybe as a field in CPUArchState or > some parent QOM machine as only i386, hppa, loongarch, riscv, alpha > actually use the definition. A fair few of these are arguably wrong. > hw/loongarch/boot.c: return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS); > -- > hw/loongarch/boot.c- *kernel_entry = extract64(le64_to_cpu(hdr->kernel_entry), > hw/loongarch/boot.c: 0, TARGET_PHYS_ADDR_SPACE_BITS); > hw/loongarch/boot.c- *kernel_low = extract64(le64_to_cpu(hdr->load_offset), > hw/loongarch/boot.c: 0, TARGET_PHYS_ADDR_SPACE_BITS); This is cpu_loongarch_virt_to_phys, and some repetitions. This should probably use a loongarch-specific runtime function to find the address space range supported by the chosen cpu. Or perhaps just a target-specific constant mask. > linux-user/alpha/target_proc.h- "L3 cache\t\t: n/a\n", > linux-user/alpha/target_proc.h: model, TARGET_PAGE_SIZE, TARGET_PHYS_ADDR_SPACE_BITS, > linux-user/alpha/target_proc.h- max_cpus, num_cpus, cpu_mask); This is the alpha-linux-user implementation of /proc/cpuinfo. Ideally this should be a target-specific function; see /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ #define TARGET_PHYS_ADDR_SPACE_BITS 44 It's certainly not generic, and it's also not really important. > -- > target/hppa/mem_helper.c: QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 54); > target/hppa/mem_helper.c: return sextract64(addr, 0, TARGET_PHYS_ADDR_SPACE_BITS); > -- > target/hppa/mem_helper.c: addr |= -1ull << (TARGET_PHYS_ADDR_SPACE_BITS - 4); > -- > target/hppa/mem_helper.c- /* Ignore the bits beyond physical address space. */ > target/hppa/mem_helper.c: ent->pa = sextract64(ent->pa, 0, TARGET_PHYS_ADDR_SPACE_BITS); Similarly /* ??? PA-8000 through 8600 have 40 bits; PA-8700 and 8900 have 44 bits. */ # define TARGET_PHYS_ADDR_SPACE_BITS 40 While we don't actually name concrete cpu models, bios advertises the (32-bit) HP B160L machine, which originally had a 7300LC, and the (64-bit) which had a 8700. I can't find definitive documentation, but I suspect the 7300LC has only 32 physical address bits. And according to our own comment we get the 8700 value wrong. In either case, it's not exposed to generic code. > -- > target/i386/cpu.c- if (cpu->phys_bits && > target/i386/cpu.c: (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || > target/i386/cpu.c- cpu->phys_bits < 32)) { > -- > target/i386/cpu.c- " (but is %u)", > target/i386/cpu.c: TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); > -- > target/i386/kvm/kvm.c: QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); > target/i386/kvm/kvm.c: assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); All of these are simply making sure that cpu->phys_bits is "in range", which is now irrelevant because TARGET_PHYS_ADDR_SPACE_BITS itself is no longer in use. They can all be removed. > -- > target/i386/tcg/helper-tcg.h:QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS); Likewise. > target/loongarch/internals.h:#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS) This is used by target/loongarch/tcg/tlb_helper.c. I'm not sure what the implications are. Should it be using a common function with the loongarch boot virt-to-phys? Is it re-using TARGET_PHYS_ADDR_SPACE_BITS just because it was convienient? In either case, it's not exposed to generic code. r~