From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"cfu@mips.com" <cfu@mips.com>, "mst@redhat.com" <mst@redhat.com>,
"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
"dbarboza@ventanamicro.com" <dbarboza@ventanamicro.com>,
Thomas Huth <thuth@redhat.com>
Subject: Re: [PATCH v6 14/14] test/functional: Add test for boston-aia board
Date: Fri, 8 Aug 2025 18:32:59 +0200 [thread overview]
Message-ID: <8f2db989-df19-4fb3-b58e-151bd175d57e@linaro.org> (raw)
In-Reply-To: <20250717093833.402237-15-djordje.todorovic@htecgroup.com>
Hi,
On 17/7/25 11:38, Djordje Todorovic wrote:
> Add functional test for Boston AIA board. The P8700 RISC-V based
> CPU by MIPS supports it at the moment.
>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
> tests/functional/meson.build | 1 +
> tests/functional/test_riscv64_boston.py | 78 +++++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
> create mode 100755 tests/functional/test_riscv64_boston.py
> diff --git a/tests/functional/test_riscv64_boston.py b/tests/functional/test_riscv64_boston.py
> new file mode 100755
> index 0000000000..eb5dd07b79
> --- /dev/null
> +++ b/tests/functional/test_riscv64_boston.py
> @@ -0,0 +1,78 @@
> +#!/usr/bin/env python3
> +#
> +# Boston board test for RISC-V P8700 processor by MIPS
> +#
> +# Copyright (c) 2025 MIPS
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +
> +from qemu_test import QemuSystemTest
> +
> +class RiscvBostonTest(QemuSystemTest):
> + """
> + Test the boston-aia board with P8700 processor
> + """
> +
> + timeout = 10
> +
> + def test_boston_memory_constraints(self):
> + """
> + Test that boston-aia board enforces memory size constraints
> + """
> + # Test invalid memory size
> + self.set_machine('boston-aia')
> + self.vm.add_args('-cpu', 'mips-p8700')
> + self.vm.add_args('-m', '512M') # Invalid size
> + self.vm.add_args('-nographic')
> + self.vm.set_qmp_monitor(enabled=False)
> + self.vm.launch()
> + self.vm.wait()
> +
> + # Should fail due to invalid memory size
> + self.assertEqual(self.vm.exitcode(), 1)
> + log = self.vm.get_log()
> + self.assertIn("Memory size must be 1GB, 2GB, 3GB, or 4GB", log)
> +
> + def test_boston_requires_kernel(self):
> + """
> + Test that boston-aia board requires a kernel or bios
> + """
> + self.set_machine('boston-aia')
> + self.vm.add_args('-cpu', 'mips-p8700')
> + self.vm.add_args('-m', '1G') # Valid size
> + self.vm.add_args('-nographic')
> + # No kernel or bios specified
> + self.vm.set_qmp_monitor(enabled=False)
> + self.vm.launch()
> + self.vm.wait()
> +
> + # Should fail due to missing kernel/bios
> + self.assertEqual(self.vm.exitcode(), 1)
> + log = self.vm.get_log()
> + self.assertIn("Please provide either a -kernel or -bios argument", log)
> +
> + def test_boston_cpu_count(self):
> + """
> + Test various CPU counts for boston-aia board
> + """
> + cpu_counts = [1, 2, 4, 8]
> +
> + for cpus in cpu_counts:
> + with self.subTest(cpus=cpus):
> + self.set_machine('boston-aia')
> + self.vm.add_args('-cpu', 'mips-p8700')
> + self.vm.add_args('-smp', str(cpus))
> + self.vm.add_args('-m', '1G')
> + self.vm.add_args('-nographic')
> + self.vm.set_qmp_monitor(enabled=False)
> + self.vm.launch()
> + self.vm.wait()
> +
> + # Board should fail due to missing kernel, not CPU count
> + self.assertEqual(self.vm.exitcode(), 1)
> + log = self.vm.get_log()
> + self.assertIn("Please provide either a -kernel or -bios argument", log)
> +
> +if __name__ == '__main__':
> + QemuSystemTest.main()
Thanks for testing these constraints, but can we have guest code
actually exercising the code path to the XMIPS instructions?
Also code testing powering VPs up/down, to cover CPS, GCR and CPC.
Code using the e1000e card would be awesome ;)
Thanks,
Phil.
next prev parent reply other threads:[~2025-08-08 16:33 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-17 9:38 [PATCH v6 00/14] riscv: Add support for MIPS P8700 CPU Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 01/14] hw/intc: Allow gaps in hartids for aclint and aplic Djordje Todorovic
2025-08-08 15:52 ` Philippe Mathieu-Daudé
2025-09-01 8:17 ` Djordje Todorovic
2025-09-01 11:05 ` Philippe Mathieu-Daudé
2025-09-03 12:35 ` Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 02/14] target/riscv: Add cpu_set_exception_base Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 04/14] target/riscv: Add MIPS P8700 CSRs Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 03/14] target/riscv: Add MIPS P8700 CPU Djordje Todorovic
2025-08-08 17:02 ` Philippe Mathieu-Daudé
2025-09-01 8:17 ` Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 05/14] target/riscv: Add mips.ccmov instruction Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 06/14] target/riscv: Add mips.pref instruction Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 08/14] hw/misc: Add RISC-V CMGCR device implementation Djordje Todorovic
2025-08-08 16:00 ` Philippe Mathieu-Daudé
2025-08-08 16:07 ` Philippe Mathieu-Daudé
2025-09-01 8:24 ` Djordje Todorovic
2025-09-01 10:53 ` Philippe Mathieu-Daudé
2025-09-01 8:24 ` Djordje Todorovic
2025-08-08 16:05 ` Philippe Mathieu-Daudé
2025-09-01 8:22 ` Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 09/14] hw/misc: Add RISC-V CPC " Djordje Todorovic
2025-08-08 16:21 ` Philippe Mathieu-Daudé
2025-07-17 9:38 ` [PATCH v6 07/14] target/riscv: Add Xmipslsp instructions Djordje Todorovic
2025-08-08 16:02 ` Philippe Mathieu-Daudé
2025-09-01 8:20 ` Djordje Todorovic
2025-09-01 8:30 ` Djordje Todorovic
2025-09-01 11:09 ` Philippe Mathieu-Daudé
2025-07-17 9:38 ` [PATCH v6 10/14] hw/riscv: Add support for RISCV CPS Djordje Todorovic
2025-08-08 16:26 ` Philippe Mathieu-Daudé
2025-09-01 8:30 ` Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 11/14] hw/riscv: Add support for MIPS Boston-aia board mode Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 13/14] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 12/14] hw/pci: Allow explicit function numbers in pci Djordje Todorovic
2025-08-08 16:29 ` Philippe Mathieu-Daudé
2025-09-01 8:31 ` Djordje Todorovic
2025-07-17 9:38 ` [PATCH v6 14/14] test/functional: Add test for boston-aia board Djordje Todorovic
2025-08-08 16:32 ` Philippe Mathieu-Daudé [this message]
2025-09-01 8:35 ` Djordje Todorovic
2025-08-05 10:10 ` [PATCH v6 00/14] riscv: Add support for MIPS P8700 CPU Djordje Todorovic
2025-08-07 18:35 ` Daniel Henrique Barboza
2025-09-01 8:07 ` Djordje Todorovic
2025-08-08 16:42 ` Philippe Mathieu-Daudé
2025-09-01 8:15 ` Djordje Todorovic
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