Re: [Qemu-devel] [PULL 23/44] target/ppc: Use vector variable shifts for VSL, VSR, VSRA

[Laurent Vivier <lvivier@redhat.com>]

On 11/06/2019 09:05, Laurent Vivier wrote:
> On 11/06/2019 04:43, David Gibson wrote:
>> On Fri, Jun 07, 2019 at 09:28:49AM -0500, Richard Henderson wrote:
>>> On 6/7/19 9:09 AM, Laurent Vivier wrote:
>>>> On 07/06/2019 11:29, Laurent Vivier wrote:
>>>>> On 29/05/2019 08:49, David Gibson wrote:
>>>>>> From: Richard Henderson <richard.henderson@linaro.org>
>>>>>>
>>>>>> The gvec expanders take care of masking the shift amount
>>>>>> against the element width.
>>>>>>
>>>>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>>>>> Message-Id: <20190518191430.21686-2-richard.henderson@linaro.org>
>>>>>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>>>>>> ---
>>>>>>  target/ppc/helper.h                 | 12 ----------
>>>>>>  target/ppc/int_helper.c             | 37 -----------------------------
>>>>>>  target/ppc/translate/vmx-impl.inc.c | 24 +++++++++----------
>>>>>>  3 files changed, 12 insertions(+), 61 deletions(-)
>>>>>
>>>>> This patch introduces a regressions
>>>>>  with Fedora 29 guest:
>>>>>
>>>>> - during kernel boot:
>>>>>
>>>>> [   40.397876] crypto_register_alg 'aes' = 0
>>>>> [   40.577517] crypto_register_alg 'cbc(aes)' = 0
>>>>> [   40.743576] crypto_register_alg 'ctr(aes)' = 0
>>>>> [   41.061379] alg: skcipher: Test 1 failed (invalid result) on encryption for p8_aes_xts
>>>>> [   41.062054] 00000000: 91 7c f6 9e bd 68 b2 ec 9b 9f e9 a3 ea dd a6 92
>>>>> [   41.062163] 00000010: 98 10 35 57 5e dc 36 1e 9a f7 bc ba 39 f2 5c eb
>>>>> [   41.062834] crypto_register_alg 'xts(aes)' = 0
>>>>> [   41.077358] alg: hash: Test 2 failed for p8_ghash
>>>>> [   41.077553] 00000000: 5f 89 ab f7 20 57 20 57 20 57 20 57 20 57 20 57
>>>>>
>>>>> - with libssl:
>>>>>
>>>>> # curl -o /dev/null https://www.google.com
>>>>>   % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current
>>>>>                                  Dload  Upload   Total   Spent    Left  Speed
>>>>>   0     0    0     0    0     0      0      0 --:--:-- --:--:-- --:--:--     0
>>>>> curl: (35) error:1408F119:SSL routines:ssl3_get_record:decryption failed or bad record mac
>>>>>
>>>>> [before, this one fails with:
>>>>> curl: (35) error:04091068:rsa routines:int_rsa_verify:bad signature ]
>>>>>
>>>>> If I revert this patch on top of 0d74f3b427 + "target/ppc: Fix lxvw4x, lxvh8x and lxvb16x", all works fine.
>>>>>
>>>>> Thanks,
>>>>> Laurent
>>>>>
>>>>
>>>> This seems to fix the problem:
>>>>
>>>> diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
>>>> index 3b6052fe97..6f0709b307 100644
>>>> --- a/accel/tcg/tcg-runtime-gvec.c
>>>> +++ b/accel/tcg/tcg-runtime-gvec.c
>>>> @@ -874,7 +874,7 @@ void HELPER(gvec_sar8v)(void *d, void *a, void *b,
>>>> uint32_t desc)
>>>>      intptr_t oprsz = simd_oprsz(desc);
>>>>      intptr_t i;
>>>>
>>>> -    for (i = 0; i < oprsz; i += sizeof(vec8)) {
>>>> +    for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
>>>>          uint8_t sh = *(uint8_t *)(b + i) & 7;
>>>>          *(int8_t *)(d + i) = *(int8_t *)(a + i) >> sh;
>>>>      }
>>>
>>> Grr.  I really really need to come up with a solution for testing that allows
>>> me to test paths that the host cpu would not ordinarily take.  This bug is
>>> hidden on a host with AVX2.
>>>
>>> Thanks for the digging.
>>
>> Can one of you send this fix formally with a S-o-b and so forth?
> 
> I'm going to send it.

Richard already sent it:

  [PATCH] tcg: Fix typos in helper_gvec_sar{8,32,64}v
  <20190607183016.8285-1-richard.henderson@linaro.org>

Thanks,
Laurent