* [Qemu-devel] [PATCH] PCI: PCIe access should always be little endian
@ 2017-08-15 14:44 Matt Redfearn
2017-08-16 10:25 ` Marcel Apfelbaum
0 siblings, 1 reply; 4+ messages in thread
From: Matt Redfearn @ 2017-08-15 14:44 UTC (permalink / raw)
To: Michael S . Tsirkin, Marcel Apfelbaum
Cc: qemu-devel, Yongbok Kim, Matt Redfearn
PCIe busses are always little endian, so set the endianness of the
memory region to little endian rather than native such that operations
work as expected on big endian targets.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
---
hw/pci/pcie_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index dcebf57ed45e..553db56778b6 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -81,7 +81,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
static const MemoryRegionOps pcie_mmcfg_ops = {
.read = pcie_mmcfg_data_read,
.write = pcie_mmcfg_data_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pcie_host_init(Object *obj)
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] PCI: PCIe access should always be little endian
2017-08-15 14:44 [Qemu-devel] [PATCH] PCI: PCIe access should always be little endian Matt Redfearn
@ 2017-08-16 10:25 ` Marcel Apfelbaum
2017-09-27 8:27 ` Matt Redfearn
0 siblings, 1 reply; 4+ messages in thread
From: Marcel Apfelbaum @ 2017-08-16 10:25 UTC (permalink / raw)
To: Matt Redfearn, Michael S . Tsirkin; +Cc: qemu-devel, Yongbok Kim
On 15/08/2017 17:44, Matt Redfearn wrote:
> PCIe busses are always little endian, so set the endianness of the
> memory region to little endian rather than native such that operations
> work as expected on big endian targets.
>
> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Hi Matt,
Thanks for the patch.
> ---
>
> hw/pci/pcie_host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
> index dcebf57ed45e..553db56778b6 100644
> --- a/hw/pci/pcie_host.c
> +++ b/hw/pci/pcie_host.c
> @@ -81,7 +81,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
> static const MemoryRegionOps pcie_mmcfg_ops = {
> .read = pcie_mmcfg_data_read,
> .write = pcie_mmcfg_data_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> };
>
> static void pcie_host_init(Object *obj)
>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Thanks,
Marcel
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] PCI: PCIe access should always be little endian
2017-08-16 10:25 ` Marcel Apfelbaum
@ 2017-09-27 8:27 ` Matt Redfearn
2017-09-29 12:37 ` Marcel Apfelbaum
0 siblings, 1 reply; 4+ messages in thread
From: Matt Redfearn @ 2017-09-27 8:27 UTC (permalink / raw)
To: Marcel Apfelbaum, Michael S . Tsirkin; +Cc: qemu-devel, Yongbok Kim
ping?
On 16/08/17 11:25, Marcel Apfelbaum wrote:
> On 15/08/2017 17:44, Matt Redfearn wrote:
>> PCIe busses are always little endian, so set the endianness of the
>> memory region to little endian rather than native such that operations
>> work as expected on big endian targets.
>>
>> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
>
>
> Hi Matt,
> Thanks for the patch.
>
>> ---
>>
>> hw/pci/pcie_host.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
>> index dcebf57ed45e..553db56778b6 100644
>> --- a/hw/pci/pcie_host.c
>> +++ b/hw/pci/pcie_host.c
>> @@ -81,7 +81,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
>> static const MemoryRegionOps pcie_mmcfg_ops = {
>> .read = pcie_mmcfg_data_read,
>> .write = pcie_mmcfg_data_write,
>> - .endianness = DEVICE_NATIVE_ENDIAN,
>> + .endianness = DEVICE_LITTLE_ENDIAN,
>> };
>> static void pcie_host_init(Object *obj)
>>
>
>
> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
>
> Thanks,
> Marcel
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] PCI: PCIe access should always be little endian
2017-09-27 8:27 ` Matt Redfearn
@ 2017-09-29 12:37 ` Marcel Apfelbaum
0 siblings, 0 replies; 4+ messages in thread
From: Marcel Apfelbaum @ 2017-09-29 12:37 UTC (permalink / raw)
To: Matt Redfearn, Michael S . Tsirkin; +Cc: qemu-devel, Yongbok Kim
On 27/09/2017 11:27, Matt Redfearn wrote:
> ping?
>
Hi Matt,
I think Michael is in PTO, he'll pick up
the patch as soon he is back.
Thanks,
Marcel
>
> On 16/08/17 11:25, Marcel Apfelbaum wrote:
>> On 15/08/2017 17:44, Matt Redfearn wrote:
>>> PCIe busses are always little endian, so set the endianness of the
>>> memory region to little endian rather than native such that operations
>>> work as expected on big endian targets.
>>>
>>> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
>>
>>
>> Hi Matt,
>> Thanks for the patch.
>>
>>> ---
>>>
>>> hw/pci/pcie_host.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
>>> index dcebf57ed45e..553db56778b6 100644
>>> --- a/hw/pci/pcie_host.c
>>> +++ b/hw/pci/pcie_host.c
>>> @@ -81,7 +81,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
>>> static const MemoryRegionOps pcie_mmcfg_ops = {
>>> .read = pcie_mmcfg_data_read,
>>> .write = pcie_mmcfg_data_write,
>>> - .endianness = DEVICE_NATIVE_ENDIAN,
>>> + .endianness = DEVICE_LITTLE_ENDIAN,
>>> };
>>> static void pcie_host_init(Object *obj)
>>>
>>
>>
>> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
>>
>> Thanks,
>> Marcel
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-09-29 12:37 UTC | newest]
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2017-08-15 14:44 [Qemu-devel] [PATCH] PCI: PCIe access should always be little endian Matt Redfearn
2017-08-16 10:25 ` Marcel Apfelbaum
2017-09-27 8:27 ` Matt Redfearn
2017-09-29 12:37 ` Marcel Apfelbaum
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