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Mon, 29 May 2023 00:01:55 -0700 (PDT) Received: from [192.168.43.219] ([88.174.74.114]) by smtp.gmail.com with ESMTPSA id q13-20020a7bce8d000000b003f43f82001asm16818788wmj.31.2023.05.29.00.01.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 May 2023 00:01:55 -0700 (PDT) Message-ID: <8fb19b45-0dc3-a3d6-fcf9-5fc8728edf4d@redhat.com> Date: Mon, 29 May 2023 09:01:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH] igb: Add Function Level Reset to PF and VF Content-Language: en-US To: Akihiko Odaki , Sriram Yagnaraman , "qemu-devel@nongnu.org" Cc: Jason Wang References: <20230526173035.69055-1-clg@redhat.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.164, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.093, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/29/23 04:45, Akihiko Odaki wrote: > On 2023/05/28 19:50, Sriram Yagnaraman wrote: >> >>> -----Original Message----- >>> From: Cédric Le Goater >>> Sent: Friday, 26 May 2023 19:31 >>> To: qemu-devel@nongnu.org >>> Cc: Akihiko Odaki ; Sriram Yagnaraman >>> ; Jason Wang ; Cédric >>> Le Goater >>> Subject: [PATCH] igb: Add Function Level Reset to PF and VF >>> >>> The Intel 82576EB GbE Controller say that the Physical and Virtual Functions >>> support Function Level Reset. Add the capability to each device model. >>> >>> Cc: Akihiko Odaki >>> Fixes: 3a977deebe6b ("Intrdocue igb device emulation") >>> Signed-off-by: Cédric Le Goater >>> --- >>>   hw/net/igb.c   | 3 +++ >>>   hw/net/igbvf.c | 3 +++ >>>   2 files changed, 6 insertions(+) >>> >>> diff --git a/hw/net/igb.c b/hw/net/igb.c index 1c989d767725..08e389338dca >>> 100644 >>> --- a/hw/net/igb.c >>> +++ b/hw/net/igb.c >>> @@ -101,6 +101,7 @@ static void igb_write_config(PCIDevice *dev, uint32_t >>> addr, >>> >>>       trace_igb_write_config(addr, val, len); >>>       pci_default_write_config(dev, addr, val, len); >>> +    pcie_cap_flr_write_config(dev, addr, val, len); >>> >>>       if (range_covers_byte(addr, len, PCI_COMMAND) && >>>           (dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { @@ -427,6 >>> +428,8 @@ static void igb_pci_realize(PCIDevice *pci_dev, Error **errp) >>>       } >>> >>>       /* PCIe extended capabilities (in order) */ >>> +    pcie_cap_flr_init(pci_dev); >>> + >>>       if (pcie_aer_init(pci_dev, 1, 0x100, 0x40, errp) < 0) { >>>           hw_error("Failed to initialize AER capability"); >>>       } >>> diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c index >>> 284ea611848b..0a58dad06802 100644 >>> --- a/hw/net/igbvf.c >>> +++ b/hw/net/igbvf.c >>> @@ -204,6 +204,7 @@ static void igbvf_write_config(PCIDevice *dev, >>> uint32_t addr, uint32_t val,  { >>>       trace_igbvf_write_config(addr, val, len); >>>       pci_default_write_config(dev, addr, val, len); >>> +    pcie_cap_flr_write_config(dev, addr, val, len); >>>   } >>> >>>   static uint64_t igbvf_mmio_read(void *opaque, hwaddr addr, unsigned size) >>> @@ -266,6 +267,8 @@ static void igbvf_pci_realize(PCIDevice *dev, Error >>> **errp) >>>           hw_error("Failed to initialize PCIe capability"); >>>       } >>> >>> +    pcie_cap_flr_init(dev); >> >> Sorry for my naive question, and perhaps not related to your patch, IGBVF device class doesn't seem to have any reset functions registered via igbvf_class_init(). So, I am guessing an FLR will not trigger igb_vf_reset(), which is probably what we want. It does through the VTCTRL registers. > You're right. Advertising FLR capability without implementing it can confuse the guest though such probability is quite a low in practice. The reset should be implemented first. I was looking at an issue from a VFIO perspective which does a FLR on a device when pass through. Software and FLR are equivalent for a VF. I am not sure a VF needs more really, since it is all controlled by the PF. C. > >> >>> + >>>       if (pcie_aer_init(dev, 1, 0x100, 0x40, errp) < 0) { >>>           hw_error("Failed to initialize AER capability"); >>>       } >>> -- >>> 2.40.1 >> >