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Sun, 13 Jul 2025 22:43:41 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9e06995sm9464990b3a.38.2025.07.13.22.43.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 13 Jul 2025 22:43:40 -0700 (PDT) Message-ID: <8fb88ab0-7b14-43b1-b7c9-44e597c3425c@linaro.org> Date: Sun, 13 Jul 2025 22:43:39 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 3/6] target/arm: Add FEAT_SCTLR2 To: Richard Henderson , Gustavo Romero Cc: qemu-devel References: <20250711140828.1714666-1-gustavo.romero@linaro.org> <20250711140828.1714666-4-gustavo.romero@linaro.org> <09497926-db8a-4475-b361-7e8338597326@linaro.org> <268ae2cf-503f-4a51-b644-d227417fedb2@linaro.org> Content-Language: en-US From: Pierrick Bouvier In-Reply-To: <268ae2cf-503f-4a51-b644-d227417fedb2@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/13/25 9:27 AM, Richard Henderson wrote: > On 7/11/25 23:02, Richard Henderson wrote: >> On 7/11/25 08:08, Gustavo Romero wrote: >>> Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and >>> SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx >>> ones. >>> >>> Because the bits in these registers depend on other CPU features, and >>> only FEAT_MEC is supported at the moment, this commit only implements >>> the EMEC bits in CTLR2_EL2 and SCTLR2_EL3. >>> >>> Signed-off-by: Gustavo Romero >>> Reviewed-by: Richard Henderson >>> --- >>>   docs/system/arm/emulation.rst |  1 + >>>   target/arm/cpu-features.h     |  5 +++ >>>   target/arm/cpu.c              |  3 ++ >>>   target/arm/cpu.h              | 15 +++++++ >>>   target/arm/helper.c           | 80 +++++++++++++++++++++++++++++++++++ >>>   target/arm/internals.h        |  1 + >>>   target/arm/tcg/cpu64.c        |  5 ++- >>>   7 files changed, 109 insertions(+), 1 deletion(-) >> >> Bisect points to this patch as breaking >> >> 45/60 qemu:func-thorough+func-aarch64-thorough+thorough / func-aarch64-aarch64_rme_sbsaref >>        TIMEOUT        1200.01s   killed by signal 15 SIGTERM >> 46/60 qemu:func-thorough+func-aarch64-thorough+thorough / func-aarch64-aarch64_rme_virt >>        TIMEOUT        1200.02s   killed by signal 15 SIGTERM >> >> Try make check-functional-aarch64. > > This is caused by the realm os being new enough to try to access SCTLR2, but the op-tee > firmware is not new enough to enable access to SCTLR2. So Realm EL2 unexpectedly but > correctly traps to EL3, and the whole stack gets wedged: > > 2025-07-13 10:16:12,680: SMC_RMI_REALM_ACTIVATE > 2025-07-13 10:16:12,680: 10045c6c000 > RMI_SUCCESS > 2025-07-13 10:16:12,689: Unexpected exception on CPU #0: > > Pierrick, I believe you built the rme test images. Is there perhaps a newer version of > the firmware that supports (at least) SCTLR2 and TCR2? > It seems that TF-A has an option 'ENABLE_FEAT_SCTLR2'. I will try to build with it, and current series, and see how it goes. > > r~