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Fri, 25 Jun 2021 23:06:31 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id 71sm7948241pfw.13.2021.06.25.23.06.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Jun 2021 23:06:31 -0700 (PDT) Subject: Re: [PATCH 0/5] tcg: Issue memory barriers for guest memory model From: Richard Henderson To: qemu-devel@nongnu.org References: <20210316220735.2048137-1-richard.henderson@linaro.org> Message-ID: <90884d4e-f057-5035-b21c-653ce6203a81@linaro.org> Date: Fri, 25 Jun 2021 23:06:30 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210316220735.2048137-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FUZZY_BITCOIN=1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Ping. A local rebase seems to apply clean. r~ On 3/16/21 3:07 PM, Richard Henderson wrote: > This is intending to fix the current aarch64 host failure > for s390x guest cdrom-test. This is caused by the io thread > issuing memory barriers that are supposed to be matched by > the vcpu, but are elided by tcg in rr mode as "unnecessary". > > I know Peter would like a smaller patch to sync the io thread > with the vcpu thread. I've made a couple of attempts at this, > but havn't managed to get something reliable (although now > irritatingly infrequent -- about 1 in 500). > > I have further patches to further optimize barriers, and to > generate load-acquire/store-release instructions in tcg. > But it's late in the release cycle, etc etc. > > I've done nothing to measure the performance impact of this. > I quit the cdtom-test cycle after 4000 passes. > > > r~ > > > Richard Henderson (5): > tcg: Decode the operand to INDEX_op_mb in dumps > tcg: Do not elide memory barriers for CF_PARALLEL > tcg: Elide memory barriers implied by the host memory model > tcg: Create tcg_req_mo > tcg: Add host memory barriers to cpu_ldst.h interfaces > > include/exec/cpu_ldst.h | 7 ++++ > include/tcg/tcg.h | 20 +++++++++++ > accel/tcg/cputlb.c | 2 ++ > accel/tcg/tcg-all.c | 6 +--- > accel/tcg/user-exec.c | 17 +++++++++ > tcg/tcg-op.c | 19 +++++----- > tcg/tcg.c | 79 +++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 137 insertions(+), 13 deletions(-) >