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From: shashi.mallela@linaro.org
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Eric Auger <eric.auger@redhat.com>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: SMMU Stage 2 translation in QEMU
Date: Fri, 10 Sep 2021 08:39:50 -0400	[thread overview]
Message-ID: <909bcf70ba8d88d485ec0b36371633e54edef81c.camel@linaro.org> (raw)
In-Reply-To: <CAFEAcA-k8=M5KQWoJ=yurAZuHt9=F9mb002Z=7T_EC6x5EP95w@mail.gmail.com>

I am referring to the latter,"purely emulated QEMU with an emulated
SMMU that handles accesses to emulated devices"

Thanks
Shashi

On Fri, 2021-09-10 at 10:25 +0100, Peter Maydell wrote:
> On Thu, 9 Sept 2021 at 21:18, <shashi.mallela@linaro.org> wrote:
> > I am trying to understand the approach required for an emulated
> > SMMU to
> > convert IPAs(from each qemu guest) to PAs(respective host
> > addresses)
> > using stage 2 tables.
> > 
> > The questions i have are:-
> > 
> > 1) Since SMMU stage 2 tables are expected to be created and managed
> > by
> > a hypervisor,if there is no kvm support,who is responsible to
> > create
> > the stage 2 tables in host memory? is it even a valid use case to
> > consider smmu stage 2 support with no hypervisor present?
> 
> So what exactly is the use case you're talking about here?
> Do you mean "purely emulated QEMU, but using a host hardware
> IOMMU to do device passthrough of host devices to the guest"?
> Or do you mean "purely emulated QEMU with an emulated SMMU
> that handles accesses to emulated devices" ?
> 
> thanks
> -- PMM



  reply	other threads:[~2021-09-10 12:42 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-09 20:17 SMMU Stage 2 translation in QEMU shashi.mallela
2021-09-10  9:25 ` Peter Maydell
2021-09-10 12:39   ` shashi.mallela [this message]
2021-09-10 12:54     ` Peter Maydell
2021-09-10 13:32       ` shashi.mallela
2021-09-13  8:19         ` Eric Auger
2021-09-14 15:57           ` shashi.mallela
2021-09-15 10:23             ` Eric Auger

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