From: Richard Henderson <richard.henderson@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH] target/i386: correctly mask SSE4a bit indices in register operands
Date: Tue, 20 Sep 2022 05:46:29 +0200 [thread overview]
Message-ID: <90ae9a51-07be-d12a-99bf-d829584805d9@linaro.org> (raw)
In-Reply-To: <20220918071807.539664-1-pbonzini@redhat.com>
On 9/18/22 09:18, Paolo Bonzini wrote:
> SSE4a instructions EXTRQ and INSERTQ have two bit index operands, that can be
> immediates or taken from an XMM register. In both cases, the fields are
> 6-bit wide and the top two bits in the byte are ignored. translate.c is
> doing that correctly for the immediate case, but not for the XMM case, so
> fix it.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/ops_sse.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
But these aren't SSE4a, they're AMD New Media instructions, which was a bit confusing.
r~
prev parent reply other threads:[~2022-09-20 3:47 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-18 7:18 [PATCH] target/i386: correctly mask SSE4a bit indices in register operands Paolo Bonzini
2022-09-20 3:46 ` Richard Henderson [this message]
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