From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49669) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPJPp-0004Vp-7p for qemu-devel@nongnu.org; Fri, 19 Oct 2012 16:43:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TPJPn-0006RC-T0 for qemu-devel@nongnu.org; Fri, 19 Oct 2012 16:43:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44345) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPJPn-0006Qz-JW for qemu-devel@nongnu.org; Fri, 19 Oct 2012 16:43:31 -0400 Date: Fri, 19 Oct 2012 16:43:28 -0400 From: Jason Baron Message-Id: <90e044f23b95d27e94d09e50f768b9b05258c28e.1350677361.git.jbaron@redhat.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH v3 04/26] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com, juzhang@redhat.com, mst@redhat.com, jan.kiszka@siemens.com, armbru@redhat.com, agraf@suse.de, blauwirbel@gmail.com, yamahata@valinux.co.jp, alex.williamson@redhat.com, kevin@koconnor.net, avi@redhat.com, mkletzan@redhat.com, pbonzini@redhat.com, lcapitulino@redhat.com, afaerber@suse.de, kraxel@redhat.com From: Isaku Yamahata Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is standardized. PCI bridge swizzle is common logic, by introducing this function duplicated swizzle logic will be avoided later. [jbaron@redhat.com: drop opaque argument] Reviewed-by: Paolo Bonzini Signed-off-by: Isaku Yamahata Signed-off-by: Jason Baron --- hw/pci.c | 18 ++++++++++++++++++ hw/pci.h | 2 ++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index b1b105d..0bcb45e 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -1121,6 +1121,24 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev, dev->intx_routing_notifier = notifier; } +/* + * PCI-to-PCI bridge specification + * 9.1: Interrupt routing. Table 9-1 + * + * the PCI Express Base Specification, Revision 2.1 + * 2.2.8.1: INTx interrutp signaling - Rules + * the Implementation Note + * Table 2-20 + */ +/* + * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD + * 0-origin unlike PCI interrupt pin register. + */ +int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) +{ + return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; +} + /***********************************************************/ /* monitor info on PCI */ diff --git a/hw/pci.h b/hw/pci.h index d50d26c..c3c9065 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -316,6 +316,8 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, int nirq); int pci_bus_get_irq_level(PCIBus *bus, int irq_num); void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); +/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ +int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); PCIBus *pci_register_bus(DeviceState *parent, const char *name, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, -- 1.7.1