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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a892e59736sm12227960f8f.74.2025.06.30.23.31.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Jun 2025 23:31:25 -0700 (PDT) Message-ID: <90fc6fd8-fe67-4a16-b287-69da9861f180@redhat.com> Date: Tue, 1 Jul 2025 08:31:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 01/11] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association Content-Language: en-US To: Shameerali Kolothum Thodi , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "ddutile@redhat.com" , "berrange@redhat.com" , "imammedo@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , "gustavo.romero@linaro.org" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" References: <20250623094230.76084-1-shameerali.kolothum.thodi@huawei.com> <20250623094230.76084-2-shameerali.kolothum.thodi@huawei.com> <5a0ee9d2e27e47e6a4b443ef6e645b52@huawei.com> From: Eric Auger In-Reply-To: <5a0ee9d2e27e47e6a4b443ef6e645b52@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.237, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/30/25 9:01 AM, Shameerali Kolothum Thodi wrote: > Hi Eric, > >> -----Original Message----- >> From: Eric Auger >> Sent: Friday, June 27, 2025 12:52 PM >> To: Shameerali Kolothum Thodi >> ; qemu-arm@nongnu.org; >> qemu-devel@nongnu.org >> Cc: peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com; >> ddutile@redhat.com; berrange@redhat.com; imammedo@redhat.com; >> nathanc@nvidia.com; mochs@nvidia.com; smostafa@google.com; >> gustavo.romero@linaro.org; Linuxarm ; Wangzhou >> (B) ; jiangkunkun ; >> Jonathan Cameron ; >> zhangfei.gao@linaro.org >> Subject: Re: [PATCH v5 01/11] hw/arm/smmu-common: Check SMMU has >> PCIe Root Complex association >> >> Hi Shameer, >> >> On 6/23/25 11:42 AM, Shameer Kolothum wrote: >>> We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra >>> root complexes to be associated with SMMU. >>> >>> Although this change does not affect functionality at present, it is >>> required when we add support for user-creatable SMMUv3 devices in >>> future patches. >>> >>> Signed-off-by: Shameer Kolothum >> >>> --- >>> hw/arm/smmu-common.c | 29 ++++++++++++++++++++++++++--- >>> hw/pci-bridge/pci_expander_bridge.c | 1 - >>> include/hw/pci/pci_bridge.h | 1 + >>> 3 files changed, 27 insertions(+), 4 deletions(-) >>> >>> diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c >>> index f39b99e526..b15e7fd0e4 100644 >>> --- a/hw/arm/smmu-common.c >>> +++ b/hw/arm/smmu-common.c >>> @@ -20,6 +20,7 @@ >>> #include "trace.h" >>> #include "exec/target_page.h" >>> #include "hw/core/cpu.h" >>> +#include "hw/pci/pci_bridge.h" >>> #include "hw/qdev-properties.h" >>> #include "qapi/error.h" >>> #include "qemu/jhash.h" >>> @@ -925,6 +926,7 @@ static void smmu_base_realize(DeviceState *dev, >> Error **errp) >>> { >>> SMMUState *s = ARM_SMMU(dev); >>> SMMUBaseClass *sbc = ARM_SMMU_GET_CLASS(dev); >>> + PCIBus *pci_bus = s->primary_bus; >>> Error *local_err = NULL; >>> >>> sbc->parent_realize(dev, &local_err); >>> @@ -937,11 +939,32 @@ static void smmu_base_realize(DeviceState >> *dev, Error **errp) >>> g_free, g_free); >>> s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL); >>> >>> - if (s->primary_bus) { >>> - pci_setup_iommu(s->primary_bus, &smmu_ops, s); >>> - } else { >>> + if (!pci_bus) { >>> error_setg(errp, "SMMU is not attached to any PCI bus!"); >>> + return; >>> + } >>> + >>> + /* >>> + * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based >> extra >>> + * root complexes to be associated with SMMU. >>> + */ >>> + if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) && >>> + object_dynamic_cast(OBJECT(pci_bus)->parent, >> TYPE_PCI_HOST_BRIDGE)) { >>> + /* >>> + * For pxb-pcie, parent_dev will be set. Make sure it is >>> + * pxb-pcie indeed. >>> + */ >>> + if (pci_bus->parent_dev) { >>> + if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS)) { >>> + goto out_err; >>> + } >> I still wonder whether the above check was mandated as it works for what >> it is meant: > Added that check to make sure we don't support pxb-cxl which is of type > PCI_HOST_BRIDGE. Once the cxl support for ARM is up streamed and tested > with SMMUv3, we can relax this if required. agreed. I would add this in the commit msg while rebasing. Eric > >> Reviewed-by: Eric Auger > Thanks, > Shameer >