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Mon, 03 Jun 2024 08:26:31 -0700 (PDT) Message-ID: <910d4931-4e03-446c-8ff2-d4ec41944fbb@linaro.org> Date: Mon, 3 Jun 2024 17:26:29 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] mips64el-softmmu: Enable MTTCG To: =?UTF-8?Q?Alex_Benn=C3=A9e?= , Jiaxun Yang , qemu-devel@nongnu.org References: <20240511-mips_mttcg-v1-1-1b71d9b85234@flygoat.com> Content-Language: en-US Cc: Pierrick Bouvier , Anton Johansson From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240511-mips_mttcg-v1-1-1b71d9b85234@flygoat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org +Alex, Pierrick & Anton On 11/5/24 22:26, Jiaxun Yang wrote: > MTTCG was disabled in a092a9554771 ("configure: disable MTTCG > for MIPS guests") due to test case instability. > > I was able to reproduce this issue with in latest QEMU and look > into reason behind that. > > What actually happend is kernel's CP0 timer synchronisation > mechanism assumed a consistent latency in memory access between > cores, which TCG can't guarantee. Thus there is a huge drift in > count value between cores, and in early kernel versions CP0 timer > is always used as sched_clock. > > sched_clock drift back on some cores triggered RCU watchdog in > some extreme cases. > > This can be resolved by setting clocksource to MIPS, which allows > clocksource to drift together with sched_clock. However this will > leed to other problems after boot. > > Another option would beupdating kernel to later version, which > will use GIC as sched_clock. > > In non-MTTCG build, the execution is slow enough so kernel won't > observe back drifts. > > Test results: > > With clocksource=MIPS > ``` > ~/tmp/retry/retry.py -n 100 -c -- ./qemu-system-mips64el \ > -display none -vga none -serial mon:stdio \ > -machine malta -kernel ./vmlinux-4.7.0-rc1.I6400 \ > -cpu I6400 -smp 8 -vga std \ > -append "printk.time=0 clocksource=MIPS console=tty0 console=ttyS0 panic=-1" \ > --no-reboot > > 100, 0, PASS, 5.258126, 100, 100, - > Results summary: > 0: 100 times (100.00%), avg time 6.508 (55.53 varience/7.45 deviation) > Ran command 100 times, 100 passes > ``` > > With linux-next: > ``` > ~/tmp/retry/retry.py -n 100 -c -- ./qemu-system-mips64el \ > -display none -vga none -serial mon:stdio \ > -machine malta -kernel ~/linux-next/vmlinux \ > -cpu I6400 -smp 8 -vga std \ > -append "printk.time=0 console=tty0 console=ttyS0 panic=-1" \ > --no-reboot > > 100, 0, PASS, 4.507921, 100, 100, - > Results summary: > 0: 100 times (100.00%), avg time 4.233 (0.04 varience/0.21 deviation) > Ran command 100 times, 100 passes > ``` > > Signed-off-by: Jiaxun Yang > --- > I'll leave the test case alone as it's already marked as QEMU_TEST_FLAKY_TESTS > --- > configs/targets/mips64el-softmmu.mak | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/targets/mips64el-softmmu.mak b/configs/targets/mips64el-softmmu.mak > index 8d9ab3ddc4b1..199b1d909a7d 100644 > --- a/configs/targets/mips64el-softmmu.mak > +++ b/configs/targets/mips64el-softmmu.mak > @@ -1,3 +1,4 @@ > TARGET_ARCH=mips64 > TARGET_BASE_ARCH=mips > +TARGET_SUPPORTS_MTTCG=y > TARGET_NEED_FDT=y > > --- > base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5 > change-id: 20240511-mips_mttcg-47a6b19074b3 > > Best regards,