[Qemu-devel] [PATCH v3 0/2] hw/pci: PCI resource reserve capability

[Qemu-devel] [PATCH v3 0/2] hw/pci: PCI resource reserve capability

[Jing Liu]

This patch serial is about PCI resource reserve capability.

First patch refactors the resource reserve fields in GenPCIERoorPort
structure out to another new structure, called "PCIResReserve". Modify
the parameter list of pci_bridge_qemu_reserve_cap_init().

Second patch enables the resource reserve capability for legacy PCI bridge
so that firmware can reserve additional resources for this bridge.

Change Logs:
v3 -> v2
* remove the teardown patch because only need pci_del_capability
* keep the names to be consistent with firmware counterpart
* some minor fixes

v2 -> v1
* add refactoring patch
* add teardown function
* some other fixes

Jing Liu (2):
  hw/pci: factor PCI reserve resources to a separate structure
  hw/pci: add PCI resource reserve capability to legacy PCI bridge

 hw/pci-bridge/gen_pcie_root_port.c | 33 +++++++++++++++++----------------
 hw/pci-bridge/pci_bridge_dev.c     | 24 ++++++++++++++++++++++++
 hw/pci/pci_bridge.c                | 38 +++++++++++++++++---------------------
 include/hw/pci/pci_bridge.h        | 18 +++++++++++++-----
 4 files changed, 71 insertions(+), 42 deletions(-)

-- 
1.8.3.1

[Qemu-devel] [PATCH v3 1/2] hw/pci: factor PCI reserve resources to a separate structure

[Jing Liu]

Factor "bus_reserve", "io_reserve", "mem_reserve", "pref32_reserve"
and "pref64_reserve" fields of the "GenPCIERootPort" structure out
to "PCIResReserve" structure, so that other PCI bridges can
reuse it to add resource reserve capability.

Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
---
 hw/pci-bridge/gen_pcie_root_port.c | 33 +++++++++++++++++----------------
 hw/pci/pci_bridge.c                | 38 +++++++++++++++++---------------------
 include/hw/pci/pci_bridge.h        | 18 +++++++++++++-----
 3 files changed, 47 insertions(+), 42 deletions(-)

diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c
index d117e20..299de42 100644
--- a/hw/pci-bridge/gen_pcie_root_port.c
+++ b/hw/pci-bridge/gen_pcie_root_port.c
@@ -29,12 +29,8 @@ typedef struct GenPCIERootPort {
 
     bool migrate_msix;
 
-    /* additional resources to reserve on firmware init */
-    uint32_t bus_reserve;
-    uint64_t io_reserve;
-    uint64_t mem_reserve;
-    uint64_t pref32_reserve;
-    uint64_t pref64_reserve;
+    /* additional resources to reserve */
+    PCIResReserve res_reserve;
 } GenPCIERootPort;
 
 static uint8_t gen_rp_aer_vector(const PCIDevice *d)
@@ -82,16 +78,15 @@ static void gen_rp_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    int rc = pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve,
-            grp->io_reserve, grp->mem_reserve, grp->pref32_reserve,
-            grp->pref64_reserve, errp);
+    int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
+                                              grp->res_reserve, errp);
 
     if (rc < 0) {
         rpc->parent_class.exit(d);
         return;
     }
 
-    if (!grp->io_reserve) {
+    if (!grp->res_reserve.io) {
         pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
                                      PCI_COMMAND_IO);
         d->wmask[PCI_IO_BASE] = 0;
@@ -117,12 +112,18 @@ static const VMStateDescription vmstate_rp_dev = {
 };
 
 static Property gen_rp_props[] = {
-    DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true),
-    DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1),
-    DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1),
-    DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1),
-    DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1),
-    DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1),
+    DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
+                     migrate_msix, true),
+    DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
+                       res_reserve.bus, -1),
+    DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
+                     res_reserve.io, -1),
+    DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
+                     res_reserve.mem_non_pref, -1),
+    DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
+                     res_reserve.mem_pref_32, -1),
+    DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
+                     res_reserve.mem_pref_64, -1),
     DEFINE_PROP_END_OF_LIST()
 };
 
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 40a39f5..08b7e44 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -411,38 +411,34 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
 
 
 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
-                                     uint32_t bus_reserve, uint64_t io_reserve,
-                                     uint64_t mem_non_pref_reserve,
-                                     uint64_t mem_pref_32_reserve,
-                                     uint64_t mem_pref_64_reserve,
-                                     Error **errp)
+                                     PCIResReserve res_reserve, Error **errp)
 {
-    if (mem_pref_32_reserve != (uint64_t)-1 &&
-        mem_pref_64_reserve != (uint64_t)-1) {
+    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
+        res_reserve.mem_pref_64 != (uint64_t)-1) {
         error_setg(errp,
                    "PCI resource reserve cap: PREF32 and PREF64 conflict");
         return -EINVAL;
     }
 
-    if (mem_non_pref_reserve != (uint64_t)-1 &&
-        mem_non_pref_reserve >= (1ULL << 32)) {
+    if (res_reserve.mem_non_pref != (uint64_t)-1 &&
+        res_reserve.mem_non_pref >= (1ULL << 32)) {
         error_setg(errp,
                    "PCI resource reserve cap: mem-reserve must be less than 4G");
         return -EINVAL;
     }
 
-    if (mem_pref_32_reserve != (uint64_t)-1 &&
-        mem_pref_32_reserve >= (1ULL << 32)) {
+    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
+        res_reserve.mem_pref_32 >= (1ULL << 32)) {
         error_setg(errp,
                    "PCI resource reserve cap: pref32-reserve  must be less than 4G");
         return -EINVAL;
     }
 
-    if (bus_reserve == (uint32_t)-1 &&
-        io_reserve == (uint64_t)-1 &&
-        mem_non_pref_reserve == (uint64_t)-1 &&
-        mem_pref_32_reserve == (uint64_t)-1 &&
-        mem_pref_64_reserve == (uint64_t)-1) {
+    if (res_reserve.bus == (uint32_t)-1 &&
+        res_reserve.io == (uint64_t)-1 &&
+        res_reserve.mem_non_pref == (uint64_t)-1 &&
+        res_reserve.mem_pref_32 == (uint64_t)-1 &&
+        res_reserve.mem_pref_64 == (uint64_t)-1) {
         return 0;
     }
 
@@ -450,11 +446,11 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
     PCIBridgeQemuCap cap = {
             .len = cap_len,
             .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
-            .bus_res = bus_reserve,
-            .io = io_reserve,
-            .mem = mem_non_pref_reserve,
-            .mem_pref_32 = mem_pref_32_reserve,
-            .mem_pref_64 = mem_pref_64_reserve
+            .bus_res = res_reserve.bus,
+            .io = res_reserve.io,
+            .mem = res_reserve.mem_non_pref,
+            .mem_pref_32 = res_reserve.mem_pref_32,
+            .mem_pref_64 = res_reserve.mem_pref_64
     };
 
     int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
index 0347da5..cdff7ed 100644
--- a/include/hw/pci/pci_bridge.h
+++ b/include/hw/pci/pci_bridge.h
@@ -133,11 +133,19 @@ typedef struct PCIBridgeQemuCap {
 
 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
 
+/*
+ * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a
+ * capability in PCI configuration space to reserve on firmware init.
+ */
+typedef struct PCIResReserve {
+    uint32_t bus;
+    uint64_t io;
+    uint64_t mem_non_pref;
+    uint64_t mem_pref_32;
+    uint64_t mem_pref_64;
+} PCIResReserve;
+
 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
-                              uint32_t bus_reserve, uint64_t io_reserve,
-                              uint64_t mem_non_pref_reserve,
-                              uint64_t mem_pref_32_reserve,
-                              uint64_t mem_pref_64_reserve,
-                              Error **errp);
+                               PCIResReserve res_reserve, Error **errp);
 
 #endif /* QEMU_PCI_BRIDGE_H */
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH v3 1/2] hw/pci: factor PCI reserve resources to a separate structure

[Marcel Apfelbaum]

On 08/21/2018 06:18 AM, Jing Liu wrote:
> Factor "bus_reserve", "io_reserve", "mem_reserve", "pref32_reserve"
> and "pref64_reserve" fields of the "GenPCIERootPort" structure out
> to "PCIResReserve" structure, so that other PCI bridges can
> reuse it to add resource reserve capability.
>
> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
> ---
>   hw/pci-bridge/gen_pcie_root_port.c | 33 +++++++++++++++++----------------
>   hw/pci/pci_bridge.c                | 38 +++++++++++++++++---------------------
>   include/hw/pci/pci_bridge.h        | 18 +++++++++++++-----
>   3 files changed, 47 insertions(+), 42 deletions(-)
>
> diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c
> index d117e20..299de42 100644
> --- a/hw/pci-bridge/gen_pcie_root_port.c
> +++ b/hw/pci-bridge/gen_pcie_root_port.c
> @@ -29,12 +29,8 @@ typedef struct GenPCIERootPort {
>   
>       bool migrate_msix;
>   
> -    /* additional resources to reserve on firmware init */
> -    uint32_t bus_reserve;
> -    uint64_t io_reserve;
> -    uint64_t mem_reserve;
> -    uint64_t pref32_reserve;
> -    uint64_t pref64_reserve;
> +    /* additional resources to reserve */
> +    PCIResReserve res_reserve;
>   } GenPCIERootPort;
>   
>   static uint8_t gen_rp_aer_vector(const PCIDevice *d)
> @@ -82,16 +78,15 @@ static void gen_rp_realize(DeviceState *dev, Error **errp)
>           return;
>       }
>   
> -    int rc = pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve,
> -            grp->io_reserve, grp->mem_reserve, grp->pref32_reserve,
> -            grp->pref64_reserve, errp);
> +    int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
> +                                              grp->res_reserve, errp);
>   
>       if (rc < 0) {
>           rpc->parent_class.exit(d);
>           return;
>       }
>   
> -    if (!grp->io_reserve) {
> +    if (!grp->res_reserve.io) {
>           pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
>                                        PCI_COMMAND_IO);
>           d->wmask[PCI_IO_BASE] = 0;
> @@ -117,12 +112,18 @@ static const VMStateDescription vmstate_rp_dev = {
>   };
>   
>   static Property gen_rp_props[] = {
> -    DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true),
> -    DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1),
> -    DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1),
> -    DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1),
> -    DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1),
> -    DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1),
> +    DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
> +                     migrate_msix, true),
> +    DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
> +                       res_reserve.bus, -1),
> +    DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
> +                     res_reserve.io, -1),
> +    DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
> +                     res_reserve.mem_non_pref, -1),
> +    DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
> +                     res_reserve.mem_pref_32, -1),
> +    DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
> +                     res_reserve.mem_pref_64, -1),
>       DEFINE_PROP_END_OF_LIST()
>   };
>   
> diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
> index 40a39f5..08b7e44 100644
> --- a/hw/pci/pci_bridge.c
> +++ b/hw/pci/pci_bridge.c
> @@ -411,38 +411,34 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
>   
>   
>   int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
> -                                     uint32_t bus_reserve, uint64_t io_reserve,
> -                                     uint64_t mem_non_pref_reserve,
> -                                     uint64_t mem_pref_32_reserve,
> -                                     uint64_t mem_pref_64_reserve,
> -                                     Error **errp)
> +                                     PCIResReserve res_reserve, Error **errp)
>   {
> -    if (mem_pref_32_reserve != (uint64_t)-1 &&
> -        mem_pref_64_reserve != (uint64_t)-1) {
> +    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
> +        res_reserve.mem_pref_64 != (uint64_t)-1) {
>           error_setg(errp,
>                      "PCI resource reserve cap: PREF32 and PREF64 conflict");
>           return -EINVAL;
>       }
>   
> -    if (mem_non_pref_reserve != (uint64_t)-1 &&
> -        mem_non_pref_reserve >= (1ULL << 32)) {
> +    if (res_reserve.mem_non_pref != (uint64_t)-1 &&
> +        res_reserve.mem_non_pref >= (1ULL << 32)) {
>           error_setg(errp,
>                      "PCI resource reserve cap: mem-reserve must be less than 4G");
>           return -EINVAL;
>       }
>   
> -    if (mem_pref_32_reserve != (uint64_t)-1 &&
> -        mem_pref_32_reserve >= (1ULL << 32)) {
> +    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
> +        res_reserve.mem_pref_32 >= (1ULL << 32)) {
>           error_setg(errp,
>                      "PCI resource reserve cap: pref32-reserve  must be less than 4G");
>           return -EINVAL;
>       }
>   
> -    if (bus_reserve == (uint32_t)-1 &&
> -        io_reserve == (uint64_t)-1 &&
> -        mem_non_pref_reserve == (uint64_t)-1 &&
> -        mem_pref_32_reserve == (uint64_t)-1 &&
> -        mem_pref_64_reserve == (uint64_t)-1) {
> +    if (res_reserve.bus == (uint32_t)-1 &&
> +        res_reserve.io == (uint64_t)-1 &&
> +        res_reserve.mem_non_pref == (uint64_t)-1 &&
> +        res_reserve.mem_pref_32 == (uint64_t)-1 &&
> +        res_reserve.mem_pref_64 == (uint64_t)-1) {
>           return 0;
>       }
>   
> @@ -450,11 +446,11 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
>       PCIBridgeQemuCap cap = {
>               .len = cap_len,
>               .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
> -            .bus_res = bus_reserve,
> -            .io = io_reserve,
> -            .mem = mem_non_pref_reserve,
> -            .mem_pref_32 = mem_pref_32_reserve,
> -            .mem_pref_64 = mem_pref_64_reserve
> +            .bus_res = res_reserve.bus,
> +            .io = res_reserve.io,
> +            .mem = res_reserve.mem_non_pref,
> +            .mem_pref_32 = res_reserve.mem_pref_32,
> +            .mem_pref_64 = res_reserve.mem_pref_64
>       };
>   
>       int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
> diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
> index 0347da5..cdff7ed 100644
> --- a/include/hw/pci/pci_bridge.h
> +++ b/include/hw/pci/pci_bridge.h
> @@ -133,11 +133,19 @@ typedef struct PCIBridgeQemuCap {
>   
>   #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
>   
> +/*
> + * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a
> + * capability in PCI configuration space to reserve on firmware init.
> + */
> +typedef struct PCIResReserve {
> +    uint32_t bus;
> +    uint64_t io;
> +    uint64_t mem_non_pref;
> +    uint64_t mem_pref_32;
> +    uint64_t mem_pref_64;
> +} PCIResReserve;
> +
>   int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
> -                              uint32_t bus_reserve, uint64_t io_reserve,
> -                              uint64_t mem_non_pref_reserve,
> -                              uint64_t mem_pref_32_reserve,
> -                              uint64_t mem_pref_64_reserve,
> -                              Error **errp);
> +                               PCIResReserve res_reserve, Error **errp);
>   
>   #endif /* QEMU_PCI_BRIDGE_H */

Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>


Thanks,
Marcel

[Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Jing Liu]

Add hint to firmware (e.g. SeaBIOS) to reserve addtional
BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
resource reserve capability deleting in pci_bridge_dev_exitfn.

Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
---
 hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
index b2d861d..97a8e8b 100644
--- a/hw/pci-bridge/pci_bridge_dev.c
+++ b/hw/pci-bridge/pci_bridge_dev.c
@@ -46,6 +46,9 @@ struct PCIBridgeDev {
     uint32_t flags;
 
     OnOffAuto msi;
+
+    /* additional resources to reserve */
+    PCIResReserve res_reserve;
 };
 typedef struct PCIBridgeDev PCIBridgeDev;
 
@@ -95,6 +98,12 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp)
         error_free(local_err);
     }
 
+    err = pci_bridge_qemu_reserve_cap_init(dev, 0,
+                                         bridge_dev->res_reserve, errp);
+    if (err) {
+        goto cap_error;
+    }
+
     if (shpc_present(dev)) {
         /* TODO: spec recommends using 64 bit prefetcheable BAR.
          * Check whether that works well. */
@@ -103,6 +112,8 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp)
     }
     return;
 
+cap_error:
+    msi_uninit(dev);
 msi_error:
     slotid_cap_cleanup(dev);
 slotid_error:
@@ -116,6 +127,8 @@ shpc_error:
 static void pci_bridge_dev_exitfn(PCIDevice *dev)
 {
     PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
+
+    pci_del_capability(dev, PCI_CAP_ID_VNDR, sizeof(PCIBridgeQemuCap));
     if (msi_present(dev)) {
         msi_uninit(dev);
     }
@@ -162,6 +175,17 @@ static Property pci_bridge_dev_properties[] = {
                             ON_OFF_AUTO_AUTO),
     DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags,
                     PCI_BRIDGE_DEV_F_SHPC_REQ, true),
+    DEFINE_PROP_UINT32("bus-reserve", PCIBridgeDev,
+                       res_reserve.bus, -1),
+    DEFINE_PROP_SIZE("io-reserve", PCIBridgeDev,
+                     res_reserve.io, -1),
+    DEFINE_PROP_SIZE("mem-reserve", PCIBridgeDev,
+                     res_reserve.mem_non_pref, -1),
+    DEFINE_PROP_SIZE("pref32-reserve", PCIBridgeDev,
+                     res_reserve.mem_pref_32, -1),
+    DEFINE_PROP_SIZE("pref64-reserve", PCIBridgeDev,
+                     res_reserve.mem_pref_64, -1),
+
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Marcel Apfelbaum]

On 08/21/2018 06:18 AM, Jing Liu wrote:
> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
> resource reserve capability deleting in pci_bridge_dev_exitfn.
>
> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
> ---
>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
>
> diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
> index b2d861d..97a8e8b 100644
> --- a/hw/pci-bridge/pci_bridge_dev.c
> +++ b/hw/pci-bridge/pci_bridge_dev.c
> @@ -46,6 +46,9 @@ struct PCIBridgeDev {
>       uint32_t flags;
>   
>       OnOffAuto msi;
> +
> +    /* additional resources to reserve */
> +    PCIResReserve res_reserve;
>   };
>   typedef struct PCIBridgeDev PCIBridgeDev;
>   
> @@ -95,6 +98,12 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp)
>           error_free(local_err);
>       }
>   
> +    err = pci_bridge_qemu_reserve_cap_init(dev, 0,
> +                                         bridge_dev->res_reserve, errp);
> +    if (err) {
> +        goto cap_error;
> +    }
> +
>       if (shpc_present(dev)) {
>           /* TODO: spec recommends using 64 bit prefetcheable BAR.
>            * Check whether that works well. */
> @@ -103,6 +112,8 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp)
>       }
>       return;
>   
> +cap_error:
> +    msi_uninit(dev);
>   msi_error:
>       slotid_cap_cleanup(dev);
>   slotid_error:
> @@ -116,6 +127,8 @@ shpc_error:
>   static void pci_bridge_dev_exitfn(PCIDevice *dev)
>   {
>       PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
> +
> +    pci_del_capability(dev, PCI_CAP_ID_VNDR, sizeof(PCIBridgeQemuCap));
>       if (msi_present(dev)) {
>           msi_uninit(dev);
>       }
> @@ -162,6 +175,17 @@ static Property pci_bridge_dev_properties[] = {
>                               ON_OFF_AUTO_AUTO),
>       DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags,
>                       PCI_BRIDGE_DEV_F_SHPC_REQ, true),
> +    DEFINE_PROP_UINT32("bus-reserve", PCIBridgeDev,
> +                       res_reserve.bus, -1),
> +    DEFINE_PROP_SIZE("io-reserve", PCIBridgeDev,
> +                     res_reserve.io, -1),
> +    DEFINE_PROP_SIZE("mem-reserve", PCIBridgeDev,
> +                     res_reserve.mem_non_pref, -1),
> +    DEFINE_PROP_SIZE("pref32-reserve", PCIBridgeDev,
> +                     res_reserve.mem_pref_32, -1),
> +    DEFINE_PROP_SIZE("pref64-reserve", PCIBridgeDev,
> +                     res_reserve.mem_pref_64, -1),
> +
>       DEFINE_PROP_END_OF_LIST(),
>   };
>   

Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>

Thanks,
Marcel

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Liu, Jing2]

Hi Marcel,

On 8/21/2018 5:59 PM, Marcel Apfelbaum wrote:
> 
> 
> On 08/21/2018 06:18 AM, Jing Liu wrote:
>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>
>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>> ---
>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>   1 file changed, 24 insertions(+)
>>
[...]
> 
> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
> 
Thanks for the quick reviewing and feedback.
So could I ask what I should do now, update a new version
with your rb or just waiting for pushing, or else?

Thanks,
Jing

> Thanks,
> Marcel
> 

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Marcel Apfelbaum]

Hi Jing,

On 08/22/2018 04:53 AM, Liu, Jing2 wrote:
> Hi Marcel,
>
> On 8/21/2018 5:59 PM, Marcel Apfelbaum wrote:
>>
>>
>> On 08/21/2018 06:18 AM, Jing Liu wrote:
>>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>>
>>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>>> ---
>>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>>   1 file changed, 24 insertions(+)
>>>
> [...]
>>
>> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
>>
> Thanks for the quick reviewing and feedback.
> So could I ask what I should do now, update a new version
> with your rb or just waiting for pushing, or else?
>

You just need to wait until Michael adds the series
to his next pull request. Nothing more to do.

Thanks,
Marcel

> Thanks,
> Jing
>
>> Thanks,
>> Marcel
>>

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Liu, Jing2]

Hi Marcel,

On 8/22/2018 2:58 PM, Marcel Apfelbaum wrote:
> Hi Jing,
> 
> On 08/22/2018 04:53 AM, Liu, Jing2 wrote:
>> Hi Marcel,
>>
>> On 8/21/2018 5:59 PM, Marcel Apfelbaum wrote:
>>>
>>>
>>> On 08/21/2018 06:18 AM, Jing Liu wrote:
>>>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>>>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>>>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>>>
>>>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>>>> ---
>>>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>>>   1 file changed, 24 insertions(+)
>>>>
>> [...]
>>>
>>> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
>>>
>> Thanks for the quick reviewing and feedback.
>> So could I ask what I should do now, update a new version
>> with your rb or just waiting for pushing, or else?
>>
> 
> You just need to wait until Michael adds the series
> to his next pull request. Nothing more to do.
> 
OK, got it! Thanks!
BTW, do you have some suggestion on the seabios counterpart patches?
https://patchew.org/Seabios/1534386737-8131-1-git-send-email-jing2.liu@linux.intel.com/


Jing
> Thanks,
> Marcel
> 
>> Thanks,
>> Jing
>>
>>> Thanks,
>>> Marcel
>>>
> 
> 

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Marcel Apfelbaum]

Hi Jing,

On 08/24/2018 05:27 AM, Liu, Jing2 wrote:
> Hi Marcel,
>
> On 8/22/2018 2:58 PM, Marcel Apfelbaum wrote:
>> Hi Jing,
>>
>> On 08/22/2018 04:53 AM, Liu, Jing2 wrote:
>>> Hi Marcel,
>>>
>>> On 8/21/2018 5:59 PM, Marcel Apfelbaum wrote:
>>>>
>>>>
>>>> On 08/21/2018 06:18 AM, Jing Liu wrote:
>>>>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>>>>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>>>>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>>>>
>>>>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>>>>> ---
>>>>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>>>>   1 file changed, 24 insertions(+)
>>>>>
>>> [...]
>>>>
>>>> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
>>>>
>>> Thanks for the quick reviewing and feedback.
>>> So could I ask what I should do now, update a new version
>>> with your rb or just waiting for pushing, or else?
>>>
>>
>> You just need to wait until Michael adds the series
>> to his next pull request. Nothing more to do.
>>
> OK, got it! Thanks!

Please ping Michael if your code is not merged in a week or so.

> BTW, do you have some suggestion on the seabios counterpart patches?
> https://patchew.org/Seabios/1534386737-8131-1-git-send-email-jing2.liu@linux.intel.com/ 
>

I plan to have  a look this weekend.

Thanks,
Marcel

> Jing
>> Thanks,
>> Marcel
>>
>>> Thanks,
>>> Jing
>>>
>>>> Thanks,
>>>> Marcel
>>>>
>>
>>

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Liu, Jing2]

Hi Marcel,

On 8/25/2018 12:51 AM, Marcel Apfelbaum wrote:
>>>>> On 08/21/2018 06:18 AM, Jing Liu wrote:
>>>>>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>>>>>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>>>>>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>>>>>
>>>>>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>>>>>> ---
>>>>>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>>>>>   1 file changed, 24 insertions(+)
>>>>>>
>>>> [...]
>>>>>
>>>>> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
>>>>>
>>>> Thanks for the quick reviewing and feedback.
>>>> So could I ask what I should do now, update a new version
>>>> with your rb or just waiting for pushing, or else?
>>>>
>>>
>>> You just need to wait until Michael adds the series
>>> to his next pull request. Nothing more to do.
>>>
>> OK, got it! Thanks!
> 
> Please ping Michael if your code is not merged in a week or so.
> 
Got it, I will check by "git pull" to see if master branch has that.

>> BTW, do you have some suggestion on the seabios counterpart patches?
>> https://patchew.org/Seabios/1534386737-8131-1-git-send-email-jing2.liu@linux.intel.com/ 
>>
> 
> I plan to have  a look this weekend.
> 
Glad to see your comments!

Thanks very much,
Jing

> Thanks,
> Marcel
> 
>> Jing
>>> Thanks,
>>> Marcel
>>>
>>>> Thanks,
>>>> Jing
>>>>
>>>>> Thanks,
>>>>> Marcel
>>>>>
>>>
>>>
> 
> 

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Liu, Jing2]

Ping Michael :)

Thanks,
Jing

On 8/25/2018 12:51 AM, Marcel Apfelbaum wrote:
>>>>> On 08/21/2018 06:18 AM, Jing Liu wrote:
>>>>>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>>>>>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>>>>>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>>>>>
>>>>>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>>>>>> ---
>>>>>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>>>>>   1 file changed, 24 insertions(+)
[...]
>>>>> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
>>>>>
>>>> Thanks for the quick reviewing and feedback.
>>>> So could I ask what I should do now, update a new version
>>>> with your rb or just waiting for pushing, or else?
>>>>
>>>
>>> You just need to wait until Michael adds the series
>>> to his next pull request. Nothing more to do.
>>>
>> OK, got it! Thanks!
> 
> Please ping Michael if your code is not merged in a week or so.
> 
>> BTW, do you have some suggestion on the seabios counterpart patches?
>> https://patchew.org/Seabios/1534386737-8131-1-git-send-email-jing2.liu@linux.intel.com/ 
>>
> 
> I plan to have  a look this weekend.
> 
> Thanks,
> Marcel

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Liu, Jing2]

Hi Marcel and Michael,

Got no response so I would like to ask if I need do something more for
this serial? :)

Thanks,
Jing

On 8/30/2018 10:58 AM, Liu, Jing2 wrote:
> Ping Michael :)
> 
> Thanks,
> Jing
> 
> On 8/25/2018 12:51 AM, Marcel Apfelbaum wrote:
>>>>>> On 08/21/2018 06:18 AM, Jing Liu wrote:
>>>>>>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>>>>>>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>>>>>>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>>>>>>
>>>>>>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>>>>>>> ---
>>>>>>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>>>>>>   1 file changed, 24 insertions(+)
> [...]
>>>>>> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
>>>>>>
>>>>> Thanks for the quick reviewing and feedback.
>>>>> So could I ask what I should do now, update a new version
>>>>> with your rb or just waiting for pushing, or else?
>>>>>
>>>>
>>>> You just need to wait until Michael adds the series
>>>> to his next pull request. Nothing more to do.
>>>>
>>> OK, got it! Thanks!
>>
>> Please ping Michael if your code is not merged in a week or so.
>>
>>> BTW, do you have some suggestion on the seabios counterpart patches?
>>> https://patchew.org/Seabios/1534386737-8131-1-git-send-email-jing2.liu@linux.intel.com/ 
>>>
>>
>> I plan to have  a look this weekend.
>>
>> Thanks,
>> Marcel
> 

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Marcel Apfelbaum]

On 09/05/2018 05:08 AM, Liu, Jing2 wrote:
> Hi Marcel and Michael,
>
> Got no response so I would like to ask if I need do something more for
> this serial? :)
>

Hi Jing,

Maybe Michael is PTO, let's wait a few more days.

Michael, I can send a pull request for this series if you are busy.
Thanks,
Marcel

> Thanks,
> Jing
>
> On 8/30/2018 10:58 AM, Liu, Jing2 wrote:
>> Ping Michael :)
>>
>> Thanks,
>> Jing
>>
>> On 8/25/2018 12:51 AM, Marcel Apfelbaum wrote:
>>>>>>> On 08/21/2018 06:18 AM, Jing Liu wrote:
>>>>>>>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>>>>>>>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>>>>>>>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>>>>>>>
>>>>>>>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>>>>>>>> ---
>>>>>>>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>>>>>>>   1 file changed, 24 insertions(+)
>> [...]
>>>>>>> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
>>>>>>>
>>>>>> Thanks for the quick reviewing and feedback.
>>>>>> So could I ask what I should do now, update a new version
>>>>>> with your rb or just waiting for pushing, or else?
>>>>>>
>>>>>
>>>>> You just need to wait until Michael adds the series
>>>>> to his next pull request. Nothing more to do.
>>>>>
>>>> OK, got it! Thanks!
>>>
>>> Please ping Michael if your code is not merged in a week or so.
>>>
>>>> BTW, do you have some suggestion on the seabios counterpart patches?
>>>> https://patchew.org/Seabios/1534386737-8131-1-git-send-email-jing2.liu@linux.intel.com/ 
>>>>
>>>
>>> I plan to have  a look this weekend.
>>>
>>> Thanks,
>>> Marcel
>>

Re: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge

[Liu, Jing2]

Hi Marcle,

On 9/6/2018 12:36 AM, Marcel Apfelbaum wrote:
> 
> 
> On 09/05/2018 05:08 AM, Liu, Jing2 wrote:
>> Hi Marcel and Michael,
>>
>> Got no response so I would like to ask if I need do something more for
>> this serial? :)
>>
> 
> Hi Jing,
> 
> Maybe Michael is PTO, let's wait a few more days.
> 
Thank you, I got it :)

BRs,
Jing
> Michael, I can send a pull request for this series if you are busy.
> Thanks,
> Marcel
> 
>> Thanks,
>> Jing
>>
>> On 8/30/2018 10:58 AM, Liu, Jing2 wrote:
>>> Ping Michael :)
>>>
>>> Thanks,
>>> Jing
>>>
>>> On 8/25/2018 12:51 AM, Marcel Apfelbaum wrote:
>>>>>>>> On 08/21/2018 06:18 AM, Jing Liu wrote:
>>>>>>>>> Add hint to firmware (e.g. SeaBIOS) to reserve addtional
>>>>>>>>> BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
>>>>>>>>> resource reserve capability deleting in pci_bridge_dev_exitfn.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>>>>>>>>> ---
>>>>>>>>>   hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++
>>>>>>>>>   1 file changed, 24 insertions(+)
>>> [...]
>>>>>>>> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
>>>>>>>>
>>>>>>> Thanks for the quick reviewing and feedback.
>>>>>>> So could I ask what I should do now, update a new version
>>>>>>> with your rb or just waiting for pushing, or else?
>>>>>>>
>>>>>>
>>>>>> You just need to wait until Michael adds the series
>>>>>> to his next pull request. Nothing more to do.
>>>>>>
>>>>> OK, got it! Thanks!
>>>>
>>>> Please ping Michael if your code is not merged in a week or so.
>>>>
>>>>> BTW, do you have some suggestion on the seabios counterpart patches?
>>>>> https://patchew.org/Seabios/1534386737-8131-1-git-send-email-jing2.liu@linux.intel.com/ 
>>>>>
>>>>
>>>> I plan to have  a look this weekend.
>>>>
>>>> Thanks,
>>>> Marcel
>>>
> 
>