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([2400:4050:a840:1e00:78d2:b862:10a7:d486]) by smtp.gmail.com with ESMTPSA id y123-20020a636481000000b005b628aa2a8dsm65401pgb.69.2023.10.14.15.25.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Oct 2023 15:25:09 -0700 (PDT) Message-ID: <917cb69b-d97c-4f41-bf90-49ad3a42a3ba@daynix.com> Date: Sun, 15 Oct 2023 07:25:05 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] target/riscv: Initialize gdb_core_xml_file only once To: Daniel Henrique Barboza Cc: =?UTF-8?Q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , qemu-devel@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" References: <20231014033545.15220-1-akihiko.odaki@daynix.com> <20231014033545.15220-3-akihiko.odaki@daynix.com> <6a06acfc-3ca0-402e-8a98-bdd1a22bdf0d@ventanamicro.com> Content-Language: en-US From: Akihiko Odaki In-Reply-To: <6a06acfc-3ca0-402e-8a98-bdd1a22bdf0d@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=2607:f8b0:4864:20::42b; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2023/10/15 3:19, Daniel Henrique Barboza wrote: > > > On 10/14/23 00:35, Akihiko Odaki wrote: >> gdb_core_xml_file was assigned each time a CPU is instantiated before >> this change. >> >> Signed-off-by: Akihiko Odaki >> --- >>   target/riscv/cpu.c         | 5 +++++ >>   target/riscv/tcg/tcg-cpu.c | 4 ---- >>   2 files changed, 5 insertions(+), 4 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index ac4a6c7eec..a811215150 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -1575,6 +1575,11 @@ static void riscv_cpu_class_init(ObjectClass >> *c, void *data) >>       cc->get_pc = riscv_cpu_get_pc; >>       cc->gdb_read_register = riscv_cpu_gdb_read_register; >>       cc->gdb_write_register = riscv_cpu_gdb_write_register; >> +#ifdef TARGET_RISCV64 >> +    cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; >> +#elif defined(TARGET_RISCV32) >> +    cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; >> +#endif >>       cc->gdb_num_core_regs = 33; >>       cc->gdb_stop_before_watchpoint = true; >>       cc->disas_set_info = riscv_cpu_disas_set_info; >> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c >> index e0cbc56320..626fb2acea 100644 >> --- a/target/riscv/tcg/tcg-cpu.c >> +++ b/target/riscv/tcg/tcg-cpu.c >> @@ -150,8 +150,6 @@ static void >> riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) >>   static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) >>   { >> -    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); >> -    CPUClass *cc = CPU_CLASS(mcc); >>       CPURISCVState *env = &cpu->env; >>       /* Validate that MISA_MXL is set properly. */ >> @@ -159,11 +157,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU >> *cpu, Error **errp) >>   #ifdef TARGET_RISCV64 >>       case MXL_RV64: >>       case MXL_RV128: >> -        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; >>           break; >>   #elif defined(TARGET_RISCV32) >>       case MXL_RV32: >> -        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; >>           break; > > > Hmmm the issue here is that, in patch 1, you added an "elif > defined(TARGET_RISCV32)" > based on an assumption that you changed here since there's no more > gdb_core files being > set. It's opposite. Patch 1 added "elif defined(TARGET_RISCV32)" because configs/targets/riscv64-linux-user.mak and configs/targets/riscv64-softmmu.mak do not list riscv-32bit-cpu.xml and referencing it from TARGET_RISCV64 results in an error. Since patch 1 now ensures TARGET_RISCV64 will never have MXL_RV32 as misa_mxl_max, patch 2 can safely assume TARGET_RISCV64 always has riscv-64bit-cpu.xml as gdb_core_xml_file. > > My suggestion is to use patch 1 from v1, where you removed the > misa_mxl_max == misa_mxl > check at the end of this function. And then in this patch you can remove > this function > altogether since you're assigning gdb_core in riscv_cpu_class_init() and > the function will > be left doing nothing of note. Assigning gdb_core_xml_file is more like a side-effect of riscv_cpu_validate_misa_mxl(), and the main purpose of this function is to validate misa_mxl[_max]. I think it's still a good idea to validate misa_mxl_max in particular. Specifying MXL_RV32 as misa_mxl_max for TARGET_RISCV64 or specifying MXL_RV64/MXL_RV128 for TARGET_RISCV32 will not work because of the incompatible gdb_core_xml_file (and probably other reasons).