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References: <20160616060621.30422-1-haozhong.zhang@intel.com>
	<20160616060621.30422-2-haozhong.zhang@intel.com>
From: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <91a4203b-ceaa-3a0f-2a36-b7ae5b96fc42@redhat.com>
Date: Thu, 16 Jun 2016 11:50:36 +0200
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Subject: Re: [Qemu-devel] [PATCH v4 1/3] target-i386: KVM: add basic Intel
 LMCE support
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To: Haozhong Zhang <haozhong.zhang@intel.com>, qemu-devel@nongnu.org
Cc: Richard Henderson <rth@twiddle.net>, Eduardo Habkost <ehabkost@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, Marcelo Tosatti <mtosatti@redhat.com>, kvm@vger.kernel.org, Boris Petkov <bp@suse.de>, Tony Luck <tony.luck@intel.com>, Andi Kleen <andi.kleen@intel.com>, rkrcmar@redhat.com, Ashok Raj <ashok.raj@intel.com>



On 16/06/2016 08:06, Haozhong Zhang wrote:
> +            if (!lmce_supported()) {
> +                error_setg(&local_err, "KVM unavailable or LMCE not su=
pported");
> +                error_propagate(&error_abort, local_err);
> +            }

Aborts should never be triggered by user input.  The error instead
should propagate from mce_init to its caller with a new errp argument
(i.e. error_setg(errp, "KVM unavailable or LMCE not supported")).

x86_cpu_realizefn can pass &local_err and check the outcome through
local_err !=3D NULL.  See the existing call to x86_cpu_apic_create, right
above the call to mce_init.

> @@ -878,7 +891,12 @@ int kvm_arch_init_vcpu(CPUState *cs)
>      c =3D cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
>      if (c) {
>          has_msr_feature_control =3D !!(c->ecx & CPUID_EXT_VMX) ||
> -                                  !!(c->ecx & CPUID_EXT_SMX);
> +                                  !!(c->ecx & CPUID_EXT_SMX) ||
> +                                  !!(env->mcg_cap & MCG_LMCE_P);

This part is wrong; env->mcg_cap is independent from CPUID[1].ECX.

> +    }
> +
> +    if (has_msr_feature_control && (env->mcg_cap & MCG_LMCE_P)) {

Don't test has_msr_feature_control here, instead set it to true inside
the "if".

> +        has_msr_mcg_ext_ctl =3D true;
>      }
> =20
>      c =3D cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);

Which silicon has LMCE?  We may want to enable the property for some CPU
models.  Apart from this, the patch is pretty much okay.

Paolo