Re: [PATCH v6 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

[Richard Henderson <richard.henderson@linaro.org>]

On 2/27/22 04:25, Weiwei Li wrote:
>   - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
> 
> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/crypto_helper.c            | 31 +++++++++++++
>   target/riscv/helper.h                   |  5 +++
>   target/riscv/insn32.decode              |  5 +++
>   target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
>   4 files changed, 99 insertions(+)
> 
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
> index 9e56668627..f5ffc262f2 100644
> --- a/target/riscv/crypto_helper.c
> +++ b/target/riscv/crypto_helper.c
> @@ -272,4 +272,35 @@ target_ulong HELPER(aes64im)(target_ulong rs1)
>   
>       return result;
>   }
> +
> +#define ROR32(a, amt) ((a << (-amt & 31)) | (a >> (amt & 31)))

We already have a ror32 function.  However...

> +target_ulong HELPER(sha256sig0)(target_ulong rs1)
> +{
> +    uint32_t a = rs1;
> +
> +    return sext_xlen(ROR32(a, 7) ^ ROR32(a, 18) ^ (a >> 3));
> +}
> +
> +target_ulong HELPER(sha256sig1)(target_ulong rs1)
> +{
> +    uint32_t a = rs1;
> +
> +    return sext_xlen(ROR32(a, 17) ^ ROR32(a, 19) ^ (a >> 10));
> +}
> +
> +target_ulong HELPER(sha256sum0)(target_ulong rs1)
> +{
> +    uint32_t a = rs1;
> +
> +    return sext_xlen(ROR32(a, 2) ^ ROR32(a, 13) ^ ROR32(a, 22));
> +}
> +
> +target_ulong HELPER(sha256sum1)(target_ulong rs1)
> +{
> +    uint32_t a = rs1;
> +
> +    return sext_xlen(ROR32(a, 6) ^ ROR32(a, 11) ^ ROR32(a, 25));
> +}

All of these functions are quite small, and could easily be generated inline.

     tcg_gen_trunc_tl_i32(a, reg);
     tcg_gen_rotri_i32(t1, a, 7);
     tcg_gen_rotri_i32(t2, a, 18);
     tcg_gen_xor_i32(t1, t1, t2);
     tcg_gen_shri_i32(t2, a, 3);
     tcg_gen_xor_i32(t1, t1, t2);
     tcg_gen_ext_i32_tl(reg, t1);

> +static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
> +{
> +    REQUIRE_ZKNH(ctx);
> +
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> +
> +    gen_helper_sha256sig0(dest, src1);
> +    gen_set_gpr(ctx, a->rd, dest);
> +
> +    return true;
> +}

gen_unary, etc.


r~