* [PULL 00/44] target-arm queue
@ 2021-08-25 10:34 Peter Maydell
2021-08-25 17:49 ` Peter Maydell
0 siblings, 1 reply; 48+ messages in thread
From: Peter Maydell @ 2021-08-25 10:34 UTC (permalink / raw)
To: qemu-devel
First set of arm patches for 6.2. I have a lot more in my
to-review queue still...
-- PMM
The following changes since commit d42685765653ec155fdf60910662f8830bdb2cef:
Open 6.2 development tree (2021-08-25 10:25:12 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210825
for you to fetch changes up to 24b1a6aa43615be22c7ee66bd68ec5675f6a6a9a:
docs: Document how to use gdb with unix sockets (2021-08-25 10:48:51 +0100)
----------------------------------------------------------------
target-arm queue:
* More MVE emulation work
* Implement M-profile trapping on division by zero
* kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()
* hw/char/pl011: add support for sending break
* fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices
* hw/dma/pl330: Add memory region to replace default
* sbsa-ref: Rename SBSA_GWDT enum value
* fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices
* docs: Document how to use gdb with unix sockets
----------------------------------------------------------------
Eduardo Habkost (1):
sbsa-ref: Rename SBSA_GWDT enum value
Guenter Roeck (2):
fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices
fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices
Hamza Mahfooz (1):
target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()
Jan Luebbe (1):
hw/char/pl011: add support for sending break
Peter Maydell (37):
target/arm: Note that we handle VMOVL as a special case of VSHLL
target/arm: Print MVE VPR in CPU dumps
target/arm: Fix MVE VSLI by 0 and VSRI by <dt>
target/arm: Fix signed VADDV
target/arm: Fix mask handling for MVE narrowing operations
target/arm: Fix 48-bit saturating shifts
target/arm: Fix MVE 48-bit SQRSHRL for small right shifts
target/arm: Fix calculation of LTP mask when LR is 0
target/arm: Factor out mve_eci_mask()
target/arm: Fix VPT advance when ECI is non-zero
target/arm: Fix VLDRB/H/W for predicated elements
target/arm: Implement MVE VMULL (polynomial)
target/arm: Implement MVE incrementing/decrementing dup insns
target/arm: Factor out gen_vpst()
target/arm: Implement MVE integer vector comparisons
target/arm: Implement MVE integer vector-vs-scalar comparisons
target/arm: Implement MVE VPSEL
target/arm: Implement MVE VMLAS
target/arm: Implement MVE shift-by-scalar
target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats
target/arm: Implement MVE integer min/max across vector
target/arm: Implement MVE VABAV
target/arm: Implement MVE narrowing moves
target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn
target/arm: Implement MVE VMLADAV and VMLSLDAV
target/arm: Implement MVE VMLA
target/arm: Implement MVE saturating doubling multiply accumulates
target/arm: Implement MVE VQABS, VQNEG
target/arm: Implement MVE VMAXA, VMINA
target/arm: Implement MVE VMOV to/from 2 general-purpose registers
target/arm: Implement MVE VPNOT
target/arm: Implement MVE VCTP
target/arm: Implement MVE scatter-gather insns
target/arm: Implement MVE scatter-gather immediate forms
target/arm: Implement MVE interleaving loads/stores
target/arm: Re-indent sdiv and udiv helpers
target/arm: Implement M-profile trapping on division by zero
Sebastian Meyer (1):
docs: Document how to use gdb with unix sockets
Wen, Jianxian (1):
hw/dma/pl330: Add memory region to replace default
docs/system/gdb.rst | 26 +-
include/hw/arm/fsl-imx7.h | 5 +
target/arm/cpu.h | 1 +
target/arm/helper-mve.h | 283 ++++++++++
target/arm/helper.h | 4 +-
target/arm/translate-a32.h | 2 +
target/arm/vec_internal.h | 11 +
target/arm/mve.decode | 226 +++++++-
target/arm/t32.decode | 1 +
hw/arm/exynos4210.c | 3 +
hw/arm/fsl-imx6ul.c | 12 +
hw/arm/fsl-imx7.c | 7 +
hw/arm/sbsa-ref.c | 6 +-
hw/arm/xilinx_zynq.c | 3 +
hw/char/pl011.c | 6 +
hw/dma/pl330.c | 26 +-
target/arm/cpu.c | 3 +
target/arm/helper.c | 34 +-
target/arm/kvm.c | 17 +-
target/arm/m_helper.c | 4 +
target/arm/mve_helper.c | 1254 ++++++++++++++++++++++++++++++++++++++++++--
target/arm/translate-mve.c | 877 ++++++++++++++++++++++++++++++-
target/arm/translate-vfp.c | 2 +-
target/arm/translate.c | 37 +-
target/arm/vec_helper.c | 14 +-
25 files changed, 2746 insertions(+), 118 deletions(-)
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PULL 00/44] target-arm queue
2021-08-25 10:34 Peter Maydell
@ 2021-08-25 17:49 ` Peter Maydell
0 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2021-08-25 17:49 UTC (permalink / raw)
To: QEMU Developers
On Wed, 25 Aug 2021 at 11:35, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> First set of arm patches for 6.2. I have a lot more in my
> to-review queue still...
>
> -- PMM
>
> The following changes since commit d42685765653ec155fdf60910662f8830bdb2cef:
>
> Open 6.2 development tree (2021-08-25 10:25:12 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210825
>
> for you to fetch changes up to 24b1a6aa43615be22c7ee66bd68ec5675f6a6a9a:
>
> docs: Document how to use gdb with unix sockets (2021-08-25 10:48:51 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * More MVE emulation work
> * Implement M-profile trapping on division by zero
> * kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()
> * hw/char/pl011: add support for sending break
> * fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices
> * hw/dma/pl330: Add memory region to replace default
> * sbsa-ref: Rename SBSA_GWDT enum value
> * fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices
> * docs: Document how to use gdb with unix sockets
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PULL 00/44] target-arm queue
@ 2025-09-26 14:08 Peter Maydell
2025-09-26 14:08 ` [PULL 01/44] hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint Peter Maydell
` (44 more replies)
0 siblings, 45 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
Hi; here's an arm pullreq...
thanks
-- PMM
The following changes since commit 95b9e0d2ade5d633fd13ffba96a54e87c65baf39:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2025-09-24 12:04:18 -0700)
are available in the Git repository at:
https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250926
for you to fetch changes up to b71e2b281a23aca474e128a8487efb07e29f4019:
target/arm: Implement ID_AA64PFR2_EL1 (2025-09-26 13:43:33 +0100)
----------------------------------------------------------------
target-arm queue:
* reimplement VHE alias register handling
* replace magic GIC values by proper definitions
* convert power control DPRINTF() uses to trace events
* better reset related tracepoints
* implement ID_AA64PFR2_EL1
* hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint
* net/passt: Fix build failure due to missing GIO dependency
----------------------------------------------------------------
Laurent Vivier (1):
net/passt: Fix build failure due to missing GIO dependency
Peter Maydell (3):
hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint
target/arm: Move ID register field defs to cpu-features.h
target/arm: Implement ID_AA64PFR2_EL1
Philippe Mathieu-Daudé (4):
target/arm: Replace magic GIC values by proper definitions
target/arm: Convert power control DPRINTF() uses to trace events
target/arm: Trace emulated firmware reset call
target/arm: Trace vCPU reset call
Richard Henderson (36):
target/arm: Introduce KVMID_AA64_SYS_REG64
target/arm: Move compare_u64 to helper.c
target/arm/hvf: Split out sysreg.c.inc
target/arm/hvf: Reorder DEF_SYSREG arguments
target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMID
target/arm/hvf: Remove hvf_sreg_match.key
target/arm/hvf: Replace hvf_sreg_match with hvf_sreg_list
target/arm/hvf: Sort the cpreg_indexes array
target/arm/hvf: Use raw_read, raw_write to access
target/arm: Use raw_write in cp_reg_reset
target/arm: Rename all ARMCPRegInfo from opaque to ri
target/arm: Drop define_one_arm_cp_reg_with_opaque
target/arm: Restrict the scope of CPREG_FIELD32, CPREG_FIELD64
target/arm: Replace cpreg_field_is_64bit with cpreg_field_type
target/arm: Add CP_REG_AA32_64BIT_{SHIFT,MASK}
target/arm: Rename CP_REG_AA32_NS_{SHIFT,MASK}
target/arm: Convert init_cpreg_list to g_hash_table_foreach
target/arm: Remove cp argument to ENCODE_AA64_CP_REG
target/arm: Reorder ENCODE_AA64_CP_REG arguments
target/arm: Split out add_cpreg_to_hashtable_aa{32, 64}
target/arm: Improve asserts in define_one_arm_cp_reg
target/arm: Move cp processing to define_one_arm_cp_reg
target/arm: Move cpreg elimination to define_one_arm_cp_reg
target/arm: Add key parameter to add_cpreg_to_hashtable
target/arm: Split out alloc_cpreg
target/arm: Hoist the allocation of ARMCPRegInfo
target/arm: Remove name argument to alloc_cpreg
target/arm: Move alias setting for wildcards
target/arm: Move writeback of CP_ANY fields
target/arm: Move endianness fixup for 32-bit registers
target/arm: Rename TBFLAG_A64_NV2_MEM_E20 with *_E2H
target/arm: Split out redirect_cpreg
target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation
target/arm: Redirect VHE FOO_EL12 to FOO_EL1 during translation
target/arm: Rename some cpreg to their aarch64 names
target/arm: Remove define_arm_vh_e2h_redirects_aliases
meson.build | 1 +
linux-user/arm/target_proc.h | 2 +
target/arm/cpregs.h | 111 ++---
target/arm/cpu-features.h | 415 ++++++++++++++++++
target/arm/cpu.h | 413 +-----------------
target/arm/internals.h | 3 +
target/arm/kvm-consts.h | 14 +-
target/arm/tcg/translate.h | 2 +
target/arm/cpu-sysregs.h.inc | 1 +
hw/intc/arm_gicv3_cpuif.c | 10 +-
hw/usb/hcd-uhci.c | 10 +-
target/arm/arm-powerctl.c | 26 +-
target/arm/cpu.c | 16 +-
target/arm/gdbstub.c | 14 +-
target/arm/helper.c | 933 +++++++++++++++++++----------------------
target/arm/hvf/hvf.c | 240 +++--------
target/arm/kvm.c | 12 +-
target/arm/tcg/hflags.c | 8 +-
target/arm/tcg/translate-a64.c | 47 ++-
target/arm/hvf/sysreg.c.inc | 147 +++++++
target/arm/trace-events | 10 +
21 files changed, 1199 insertions(+), 1236 deletions(-)
create mode 100644 target/arm/hvf/sysreg.c.inc
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PULL 01/44] hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 02/44] net/passt: Fix build failure due to missing GIO dependency Peter Maydell
` (43 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
If the guest feeds invalid data to the UHCI controller, we
can assert:
qemu-system-x86_64: ../../hw/usb/core.c:744: usb_ep_get: Assertion `pid == USB_TOKEN_IN || pid == USB_TOKEN_OUT' failed.
(see issue 2548 for the repro case). This happens because the guest
attempts USB_TOKEN_SETUP to an endpoint other than 0, which is not
valid. The controller code doesn't catch this guest error, so
instead we hit the assertion in the USB core code.
Catch the case of SETUP to non-zero endpoint, and treat it as a fatal
error in the TD, in the same way we do for an invalid PID value in
the TD.
This is the UHCI equivalent of the same bug in OHCI that we fixed in
commit 3c3c233677 ("hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or
OUT").
This bug has been tracked as CVE-2024-8354.
Cc: qemu-stable@nongnu.org
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2548
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
---
hw/usb/hcd-uhci.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
index 4822c704f69..e207d0587a1 100644
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -735,6 +735,7 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
bool spd;
bool queuing = (q != NULL);
uint8_t pid = td->token & 0xff;
+ uint8_t ep_id = (td->token >> 15) & 0xf;
UHCIAsync *async;
async = uhci_async_find_td(s, td_addr);
@@ -778,9 +779,14 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
switch (pid) {
case USB_TOKEN_OUT:
- case USB_TOKEN_SETUP:
case USB_TOKEN_IN:
break;
+ case USB_TOKEN_SETUP:
+ /* SETUP is only valid to endpoint 0 */
+ if (ep_id == 0) {
+ break;
+ }
+ /* fallthrough */
default:
/* invalid pid : frame interrupted */
s->status |= UHCI_STS_HCPERR;
@@ -829,7 +835,7 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV,
int_mask);
}
- ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
+ ep = usb_ep_get(dev, pid, ep_id);
q = uhci_queue_new(s, qh_addr, td, ep);
}
async = uhci_async_alloc(q, td_addr);
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 02/44] net/passt: Fix build failure due to missing GIO dependency
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
2025-09-26 14:08 ` [PULL 01/44] hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 03/44] target/arm: Introduce KVMID_AA64_SYS_REG64 Peter Maydell
` (42 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Laurent Vivier <lvivier@redhat.com>
The passt networking backend uses functions from the GIO library,
such as g_subprocess_launcher_new(), to manage its daemon process.
So, building with passt enabled requires GIO to be available.
If we enable passt and disable gio the build fails during linkage with
undefined reference errors:
/usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `net_passt_start_daemon':
net/passt.c:250: undefined reference to `g_subprocess_launcher_new'
/usr/bin/ld: net/passt.c:251: undefined reference to `g_subprocess_launcher_take_fd'
/usr/bin/ld: net/passt.c:253: undefined reference to `g_subprocess_launcher_spawnv'
/usr/bin/ld: net/passt.c:256: undefined reference to `g_object_unref'
/usr/bin/ld: net/passt.c:263: undefined reference to `g_subprocess_wait'
/usr/bin/ld: net/passt.c:268: undefined reference to `g_subprocess_get_if_exited'
/usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `glib_autoptr_clear_GSubprocess':
/usr/include/glib-2.0/gio/gio-autocleanups.h:132: undefined reference to `g_object_unref'
/usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `net_passt_start_daemon':
net/passt.c:269: undefined reference to `g_subprocess_get_exit_status'
Fix this by adding an explicit weson dependency on GIO for the passt
option.
The existing dependency on linux is kept because passt is only available
on this OS.
Cc: qemu-stable@nongnu.org
Fixes: 854ee02b222 ("net: Add passt network backend")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3121
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson.build
index 72da97829ab..bdfb6214e6f 100644
--- a/meson.build
+++ b/meson.build
@@ -1280,6 +1280,7 @@ endif
enable_passt = get_option('passt') \
.require(host_os == 'linux', error_message: 'passt is supported only on Linux') \
+ .require(gio.found(), error_message: 'passt requires gio') \
.allowed()
vde = not_found
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 03/44] target/arm: Introduce KVMID_AA64_SYS_REG64
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
2025-09-26 14:08 ` [PULL 01/44] hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint Peter Maydell
2025-09-26 14:08 ` [PULL 02/44] net/passt: Fix build failure due to missing GIO dependency Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 04/44] target/arm: Move compare_u64 to helper.c Peter Maydell
` (41 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Allow us to create kvm ids directly, rather than going
through ENCODE_AA64_CP_REG + cpreg_to_kvm_id.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/kvm-consts.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index c44d23dbe79..fdb305eea1a 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -180,4 +180,15 @@ MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT);
#undef MISMATCH_CHECK
+#define KVMID_AA64_SYS_REG_(op0, op1, crn, crm, op2) \
+ (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \
+ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
+ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
+ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
+ ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
+ ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+#define KVMID_AA64_SYS_REG64(op0, op1, crn, crm, op2) \
+ (KVMID_AA64_SYS_REG_(op0, op1, crn, crm, op2) | CP_REG_SIZE_U64)
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 04/44] target/arm: Move compare_u64 to helper.c
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2025-09-26 14:08 ` [PULL 03/44] target/arm: Introduce KVMID_AA64_SYS_REG64 Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 05/44] target/arm/hvf: Split out sysreg.c.inc Peter Maydell
` (40 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
We will use this function beyond kvm.c.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 3 +++
target/arm/helper.c | 11 +++++++++++
target/arm/kvm.c | 11 -----------
3 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 0f7df97b993..1d958dbf685 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -2004,4 +2004,7 @@ void vfp_clear_float_status_exc_flags(CPUARMState *env);
void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask);
bool arm_pan_enabled(CPUARMState *env);
+/* Compare uint64_t for qsort and bsearch. */
+int compare_u64(const void *a, const void *b);
+
#endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c44294711f8..009f8d6fa1c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -40,6 +40,17 @@
static void switch_mode(CPUARMState *env, int mode);
+int compare_u64(const void *a, const void *b)
+{
+ if (*(uint64_t *)a > *(uint64_t *)b) {
+ return 1;
+ }
+ if (*(uint64_t *)a < *(uint64_t *)b) {
+ return -1;
+ }
+ return 0;
+}
+
uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
assert(ri->fieldoffset);
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index c1ec6654ca6..5a75ff59271 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -718,17 +718,6 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
memory_region_ref(kd->mr);
}
-static int compare_u64(const void *a, const void *b)
-{
- if (*(uint64_t *)a > *(uint64_t *)b) {
- return 1;
- }
- if (*(uint64_t *)a < *(uint64_t *)b) {
- return -1;
- }
- return 0;
-}
-
/*
* cpreg_values are sorted in ascending order by KVM register ID
* (see kvm_arm_init_cpreg_list). This allows us to cheaply find
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 05/44] target/arm/hvf: Split out sysreg.c.inc
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2025-09-26 14:08 ` [PULL 04/44] target/arm: Move compare_u64 to helper.c Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 06/44] target/arm/hvf: Reorder DEF_SYSREG arguments Peter Maydell
` (39 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Move the list of supported sysregs to a reuseable file.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/hvf/hvf.c | 147 ++----------------------------------
target/arm/hvf/sysreg.c.inc | 146 +++++++++++++++++++++++++++++++++++
2 files changed, 152 insertions(+), 141 deletions(-)
create mode 100644 target/arm/hvf/sysreg.c.inc
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index b77db99079e..9f8e3083b4f 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -403,150 +403,15 @@ struct hvf_sreg_match {
uint32_t cp_idx;
};
+#define DEF_SYSREG(HVF_ID, crn, crm, op0, op1, op2) \
+ { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) },
+
static struct hvf_sreg_match hvf_sreg_match[] = {
- { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 7) },
-
- { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 4) },
- { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 5) },
- { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 6) },
- { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 7) },
-
-#ifdef SYNC_NO_RAW_REGS
- /*
- * The registers below are manually synced on init because they are
- * marked as NO_RAW. We still list them to make number space sync easier.
- */
- { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) },
- { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) },
- { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) },
- { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) },
-#endif
- { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 1) },
- { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) },
- { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) },
- { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) },
- { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) },
-#ifdef SYNC_NO_MMFR0
- /* We keep the hardware MMFR0 around. HW limits are there anyway */
- { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) },
-#endif
- { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
- { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
- /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
-
- { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
- { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
- { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) },
- { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) },
- { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) },
- { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) },
-
- { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) },
- { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) },
- { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) },
- { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) },
- { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) },
- { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) },
- { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) },
- { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) },
- { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) },
- { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) },
-
- { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) },
- { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) },
- { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) },
- { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) },
- { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) },
- { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) },
- { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) },
- { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) },
- { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) },
- { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) },
- { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) },
- { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) },
- { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) },
- { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) },
- { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) },
- { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) },
- { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) },
- { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) },
- { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) },
- { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) },
+#include "sysreg.c.inc"
};
+#undef DEF_SYSREG
+
int hvf_get_registers(CPUState *cpu)
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc
new file mode 100644
index 00000000000..222698f1d19
--- /dev/null
+++ b/target/arm/hvf/sysreg.c.inc
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 0, 0, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 0, 0, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 0, 0, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 0, 0, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 0, 1, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 0, 1, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 0, 1, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 0, 1, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 0, 2, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 0, 2, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 0, 2, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 0, 2, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 0, 3, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 0, 3, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 0, 3, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 0, 3, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 0, 4, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 0, 4, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 0, 4, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 0, 4, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 0, 5, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 0, 5, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 0, 5, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 0, 5, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 0, 6, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 0, 6, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 0, 6, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 0, 6, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 0, 7, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 0, 7, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 0, 7, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 0, 7, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 0, 8, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 0, 8, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 0, 8, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 0, 8, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 0, 9, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 0, 9, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 0, 9, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 0, 9, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 0, 10, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 0, 10, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 0, 10, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 0, 10, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 0, 11, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 0, 11, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 0, 11, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 0, 11, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 0, 12, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 0, 12, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 0, 12, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 0, 12, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 0, 13, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 0, 13, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 0, 13, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 0, 13, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 0, 14, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 0, 14, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 0, 14, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 0, 14, 2, 0, 7)
+
+DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 0, 15, 2, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 0, 15, 2, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 0, 15, 2, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 0, 15, 2, 0, 7)
+
+#ifdef SYNC_NO_RAW_REGS
+/*
+ * The registers below are manually synced on init because they are
+ * marked as NO_RAW. We still list them to make number space sync easier.
+ */
+DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 0, 2, 2, 0, 0)
+DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 0, 0, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 0, 0, 3, 0, 5)
+DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 0, 4, 3, 0, 0)
+#endif
+
+DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 0, 4, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 0, 5, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 0, 5, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 0, 6, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 0, 6, 3, 0, 1)
+
+#ifdef SYNC_NO_MMFR0
+/* We keep the hardware MMFR0 around. HW limits are there anyway */
+DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 0, 7, 3, 0, 0)
+#endif
+
+DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 0, 7, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 0, 7, 3, 0, 2)
+/* Add ID_AA64MMFR3_EL1 here when HVF supports it */
+
+DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 0, 2, 2, 0, 2)
+DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 1, 0, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 1, 0, 3, 0, 2)
+DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 2, 0, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 2, 0, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_TCR_EL1, 2, 0, 3, 0, 2)
+
+DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 2, 1, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 2, 1, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 2, 1, 3, 0, 2)
+DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 2, 1, 3, 0, 3)
+DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 2, 2, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 2, 2, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 2, 2, 3, 0, 2)
+DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 2, 2, 3, 0, 3)
+DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 2, 3, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 2, 3, 3, 0, 1)
+
+DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 4, 0, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_ELR_EL1, 4, 0, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_SP_EL0, 4, 1, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 5, 1, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 5, 1, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_ESR_EL1, 5, 2, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_FAR_EL1, 6, 0, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_PAR_EL1, 7, 4, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 10, 2, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 10, 3, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 12, 0, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 13, 0, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 13, 0, 3, 0, 4)
+DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 14, 1, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 0, 0, 3, 2, 0)
+DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 13, 0, 3, 3, 2)
+DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 13, 0, 3, 3, 3)
+DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 14, 3, 3, 3, 1)
+DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 14, 3, 3, 3, 2)
+DEF_SYSREG(HV_SYS_REG_SP_EL1, 4, 1, 3, 4, 0)
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 06/44] target/arm/hvf: Reorder DEF_SYSREG arguments
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2025-09-26 14:08 ` [PULL 05/44] target/arm/hvf: Split out sysreg.c.inc Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 07/44] target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMID Peter Maydell
` (38 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
The order of the parameters in the Arm ARM is
op0, op1, crn, crm, op2
Reorder the arguments of DEF_SYSREG to match.
Mechanical change to sysreg.c.inc using
sed 's/\([^,]*\),\([^,]*\),\([^,]*\),\([^,]*\),\([^,]*\)/\1,\4,\5,\2,\3/'
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/hvf/hvf.c | 2 +-
target/arm/hvf/sysreg.c.inc | 224 ++++++++++++++++++------------------
2 files changed, 113 insertions(+), 113 deletions(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 9f8e3083b4f..f68924ba1f3 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -403,7 +403,7 @@ struct hvf_sreg_match {
uint32_t cp_idx;
};
-#define DEF_SYSREG(HVF_ID, crn, crm, op0, op1, op2) \
+#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \
{ HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) },
static struct hvf_sreg_match hvf_sreg_match[] = {
diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc
index 222698f1d19..f2276d534e6 100644
--- a/target/arm/hvf/sysreg.c.inc
+++ b/target/arm/hvf/sysreg.c.inc
@@ -1,146 +1,146 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 0, 0, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 0, 0, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 0, 0, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 0, 0, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 2, 0, 0, 0, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 2, 0, 0, 0, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 2, 0, 0, 0, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 2, 0, 0, 0, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 0, 1, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 0, 1, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 0, 1, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 0, 1, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 2, 0, 0, 1, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 2, 0, 0, 1, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 2, 0, 0, 1, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 2, 0, 0, 1, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 0, 2, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 0, 2, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 0, 2, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 0, 2, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 2, 0, 0, 2, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 2, 0, 0, 2, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 2, 0, 0, 2, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 2, 0, 0, 2, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 0, 3, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 0, 3, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 0, 3, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 0, 3, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 2, 0, 0, 3, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 2, 0, 0, 3, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 2, 0, 0, 3, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 2, 0, 0, 3, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 0, 4, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 0, 4, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 0, 4, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 0, 4, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 2, 0, 0, 4, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 2, 0, 0, 4, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 2, 0, 0, 4, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 2, 0, 0, 4, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 0, 5, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 0, 5, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 0, 5, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 0, 5, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 2, 0, 0, 5, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 2, 0, 0, 5, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 2, 0, 0, 5, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 2, 0, 0, 5, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 0, 6, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 0, 6, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 0, 6, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 0, 6, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 2, 0, 0, 6, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 2, 0, 0, 6, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 2, 0, 0, 6, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 2, 0, 0, 6, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 0, 7, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 0, 7, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 0, 7, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 0, 7, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 2, 0, 0, 7, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 2, 0, 0, 7, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 2, 0, 0, 7, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 2, 0, 0, 7, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 0, 8, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 0, 8, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 0, 8, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 0, 8, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 2, 0, 0, 8, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 2, 0, 0, 8, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 2, 0, 0, 8, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 2, 0, 0, 8, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 0, 9, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 0, 9, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 0, 9, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 0, 9, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 2, 0, 0, 9, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 2, 0, 0, 9, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 2, 0, 0, 9, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 2, 0, 0, 9, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 0, 10, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 0, 10, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 0, 10, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 0, 10, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 2, 0, 0, 10, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 2, 0, 0, 10, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 2, 0, 0, 10, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 2, 0, 0, 10, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 0, 11, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 0, 11, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 0, 11, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 0, 11, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 2, 0, 0, 11, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 2, 0, 0, 11, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 2, 0, 0, 11, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 2, 0, 0, 11, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 0, 12, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 0, 12, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 0, 12, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 0, 12, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 2, 0, 0, 12, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 2, 0, 0, 12, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 2, 0, 0, 12, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 2, 0, 0, 12, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 0, 13, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 0, 13, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 0, 13, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 0, 13, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 2, 0, 0, 13, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 2, 0, 0, 13, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 2, 0, 0, 13, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 2, 0, 0, 13, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 0, 14, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 0, 14, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 0, 14, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 0, 14, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 2, 0, 0, 14, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 2, 0, 0, 14, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 2, 0, 0, 14, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 2, 0, 0, 14, 7)
-DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 0, 15, 2, 0, 4)
-DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 0, 15, 2, 0, 5)
-DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 0, 15, 2, 0, 6)
-DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 0, 15, 2, 0, 7)
+DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 2, 0, 0, 15, 4)
+DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 2, 0, 0, 15, 5)
+DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 2, 0, 0, 15, 6)
+DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 2, 0, 0, 15, 7)
#ifdef SYNC_NO_RAW_REGS
/*
* The registers below are manually synced on init because they are
* marked as NO_RAW. We still list them to make number space sync easier.
*/
-DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 0, 2, 2, 0, 0)
-DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 0, 0, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 0, 0, 3, 0, 5)
-DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 0, 4, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 2, 0, 0, 2, 0)
+DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 3, 0, 0, 0, 0)
+DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 3, 0, 0, 0, 5)
+DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
#endif
-DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 0, 4, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 0, 5, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 0, 5, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 0, 6, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 0, 6, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
+DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
+DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
+DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
+DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
#ifdef SYNC_NO_MMFR0
/* We keep the hardware MMFR0 around. HW limits are there anyway */
-DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 0, 7, 3, 0, 0)
+DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
#endif
-DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 0, 7, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 0, 7, 3, 0, 2)
+DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
+DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
/* Add ID_AA64MMFR3_EL1 here when HVF supports it */
-DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 0, 2, 2, 0, 2)
-DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 1, 0, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 1, 0, 3, 0, 2)
-DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 2, 0, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 2, 0, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_TCR_EL1, 2, 0, 3, 0, 2)
+DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 2, 0, 0, 2, 2)
+DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 3, 0, 1, 0, 0)
+DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 3, 0, 1, 0, 2)
+DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 3, 0, 2, 0, 0)
+DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 3, 0, 2, 0, 1)
+DEF_SYSREG(HV_SYS_REG_TCR_EL1, 3, 0, 2, 0, 2)
-DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 2, 1, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 2, 1, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 2, 1, 3, 0, 2)
-DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 2, 1, 3, 0, 3)
-DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 2, 2, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 2, 2, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 2, 2, 3, 0, 2)
-DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 2, 2, 3, 0, 3)
-DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 2, 3, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 2, 3, 3, 0, 1)
+DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 3, 0, 2, 1, 0)
+DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 3, 0, 2, 1, 1)
+DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 3, 0, 2, 1, 2)
+DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 3, 0, 2, 1, 3)
+DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 3, 0, 2, 2, 0)
+DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 3, 0, 2, 2, 1)
+DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 3, 0, 2, 2, 2)
+DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 3, 0, 2, 2, 3)
+DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 3, 0, 2, 3, 0)
+DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 3, 0, 2, 3, 1)
-DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 4, 0, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_ELR_EL1, 4, 0, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_SP_EL0, 4, 1, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 5, 1, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 5, 1, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_ESR_EL1, 5, 2, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_FAR_EL1, 6, 0, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_PAR_EL1, 7, 4, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 10, 2, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 10, 3, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 12, 0, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 13, 0, 3, 0, 1)
-DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 13, 0, 3, 0, 4)
-DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 14, 1, 3, 0, 0)
-DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 0, 0, 3, 2, 0)
-DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 13, 0, 3, 3, 2)
-DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 13, 0, 3, 3, 3)
-DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 14, 3, 3, 3, 1)
-DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 14, 3, 3, 3, 2)
-DEF_SYSREG(HV_SYS_REG_SP_EL1, 4, 1, 3, 4, 0)
+DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 3, 0, 4, 0, 0)
+DEF_SYSREG(HV_SYS_REG_ELR_EL1, 3, 0, 4, 0, 1)
+DEF_SYSREG(HV_SYS_REG_SP_EL0, 3, 0, 4, 1, 0)
+DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 3, 0, 5, 1, 0)
+DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 3, 0, 5, 1, 1)
+DEF_SYSREG(HV_SYS_REG_ESR_EL1, 3, 0, 5, 2, 0)
+DEF_SYSREG(HV_SYS_REG_FAR_EL1, 3, 0, 6, 0, 0)
+DEF_SYSREG(HV_SYS_REG_PAR_EL1, 3, 0, 7, 4, 0)
+DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 3, 0, 10, 2, 0)
+DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 3, 0, 10, 3, 0)
+DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 3, 0, 12, 0, 0)
+DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 3, 0, 13, 0, 1)
+DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 3, 0, 13, 0, 4)
+DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 3, 0, 14, 1, 0)
+DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 3, 2, 0, 0, 0)
+DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 3, 3, 13, 0, 2)
+DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 3, 3, 13, 0, 3)
+DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 3, 3, 14, 3, 1)
+DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 3, 3, 14, 3, 2)
+DEF_SYSREG(HV_SYS_REG_SP_EL1, 3, 4, 4, 1, 0)
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 07/44] target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMID
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2025-09-26 14:08 ` [PULL 06/44] target/arm/hvf: Reorder DEF_SYSREG arguments Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 08/44] target/arm/hvf: Remove hvf_sreg_match.key Peter Maydell
` (37 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Conversion between KVM system registers ids and the HVF system
register ids is trivial.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/hvf/hvf.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index f68924ba1f3..7515e59c56d 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -403,6 +403,26 @@ struct hvf_sreg_match {
uint32_t cp_idx;
};
+/*
+ * QEMU uses KVM system register ids in the migration format.
+ * Conveniently, HVF uses the same encoding of the op* and cr* parameters
+ * within the low 16 bits of the ids. Thus conversion between the
+ * formats is trivial.
+ */
+
+#define KVMID_TO_HVF(KVM) ((KVM) & 0xffff)
+#define HVF_TO_KVMID(HVF) \
+ (CP_REG_ARM64 | CP_REG_SIZE_U64 | CP_REG_ARM64_SYSREG | (HVF))
+
+/* Verify this at compile-time. */
+
+#define DEF_SYSREG(HVF_ID, ...) \
+ QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));
+
+#include "sysreg.c.inc"
+
+#undef DEF_SYSREG
+
#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \
{ HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) },
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 08/44] target/arm/hvf: Remove hvf_sreg_match.key
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2025-09-26 14:08 ` [PULL 07/44] target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMID Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 09/44] target/arm/hvf: Replace hvf_sreg_match with hvf_sreg_list Peter Maydell
` (36 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Use conversion functions instead of table lookup.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/hvf/hvf.c | 35 +++++++++++++++++++----------------
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 7515e59c56d..98f49ce33a4 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -152,9 +152,6 @@ void hvf_arm_init_debug(void)
g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps);
}
-#define HVF_SYSREG(crn, crm, op0, op1, op2) \
- ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
-
#define SYSREG_OP0_SHIFT 20
#define SYSREG_OP0_MASK 0x3
#define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK)
@@ -399,7 +396,6 @@ static const struct hvf_reg_match hvf_fpreg_match[] = {
struct hvf_sreg_match {
int reg;
- uint32_t key;
uint32_t cp_idx;
};
@@ -423,8 +419,7 @@ struct hvf_sreg_match {
#undef DEF_SYSREG
-#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \
- { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) },
+#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) { HVF_ID },
static struct hvf_sreg_match hvf_sreg_match[] = {
#include "sysreg.c.inc"
@@ -469,13 +464,16 @@ int hvf_get_registers(CPUState *cpu)
pstate_write(env, val);
for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
+ int hvf_id = hvf_sreg_match[i].reg;
+ uint64_t kvm_id = HVF_TO_KVMID(hvf_id);
+
if (hvf_sreg_match[i].cp_idx == -1) {
continue;
}
if (cpu->accel->guest_debug_enabled) {
/* Handle debug registers */
- switch (hvf_sreg_match[i].reg) {
+ switch (hvf_id) {
case HV_SYS_REG_DBGBVR0_EL1:
case HV_SYS_REG_DBGBCR0_EL1:
case HV_SYS_REG_DBGWVR0_EL1:
@@ -549,8 +547,10 @@ int hvf_get_registers(CPUState *cpu)
* vCPU but simply keep the values from the previous
* environment.
*/
- const ARMCPRegInfo *ri;
- ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key);
+ uint32_t key = kvm_to_cpreg_id(kvm_id);
+ const ARMCPRegInfo *ri =
+ get_arm_cp_reginfo(arm_cpu->cp_regs, key);
+
val = read_raw_cp_reg(env, ri);
arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
@@ -559,7 +559,7 @@ int hvf_get_registers(CPUState *cpu)
}
}
- ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val);
+ ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_id, &val);
assert_hvf_ok(ret);
arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
@@ -606,13 +606,15 @@ int hvf_put_registers(CPUState *cpu)
assert(write_cpustate_to_list(arm_cpu, false));
for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
+ int hvf_id = hvf_sreg_match[i].reg;
+
if (hvf_sreg_match[i].cp_idx == -1) {
continue;
}
if (cpu->accel->guest_debug_enabled) {
/* Handle debug registers */
- switch (hvf_sreg_match[i].reg) {
+ switch (hvf_id) {
case HV_SYS_REG_DBGBVR0_EL1:
case HV_SYS_REG_DBGBCR0_EL1:
case HV_SYS_REG_DBGWVR0_EL1:
@@ -687,7 +689,7 @@ int hvf_put_registers(CPUState *cpu)
}
val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
- ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val);
+ ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_id, val);
assert_hvf_ok(ret);
}
@@ -922,14 +924,15 @@ int hvf_arch_init_vcpu(CPUState *cpu)
/* Populate cp list for all known sysregs */
for (i = 0; i < sregs_match_len; i++) {
- const ARMCPRegInfo *ri;
- uint32_t key = hvf_sreg_match[i].key;
+ int hvf_id = hvf_sreg_match[i].reg;
+ uint64_t kvm_id = HVF_TO_KVMID(hvf_id);
+ uint32_t key = kvm_to_cpreg_id(kvm_id);
+ const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
- ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
if (ri) {
assert(!(ri->type & ARM_CP_NO_RAW));
hvf_sreg_match[i].cp_idx = sregs_cnt;
- arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key);
+ arm_cpu->cpreg_indexes[sregs_cnt++] = kvm_id;
} else {
hvf_sreg_match[i].cp_idx = -1;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 09/44] target/arm/hvf: Replace hvf_sreg_match with hvf_sreg_list
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2025-09-26 14:08 ` [PULL 08/44] target/arm/hvf: Remove hvf_sreg_match.key Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 10/44] target/arm/hvf: Sort the cpreg_indexes array Peter Maydell
` (35 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Change hvf_get_registers and hvf_put_registers to iterate over
cpregs_indexes instead of hvf_sreg_match.
This lets us drop the cp_idx member of hvf_sreg_match, which leaves
only one member in the struct. Replace the struct with a const array.
Instead of int, use the proper enum type: hv_sys_reg_t.
Rename from hvf_sreg_match to hvf_sreg_list because there is no
longer any matching going on.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/hvf/hvf.c | 45 +++++++++++++++-----------------------------
1 file changed, 15 insertions(+), 30 deletions(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 98f49ce33a4..b043eac8c62 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -394,11 +394,6 @@ static const struct hvf_reg_match hvf_fpreg_match[] = {
{ HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) },
};
-struct hvf_sreg_match {
- int reg;
- uint32_t cp_idx;
-};
-
/*
* QEMU uses KVM system register ids in the migration format.
* Conveniently, HVF uses the same encoding of the op* and cr* parameters
@@ -419,9 +414,9 @@ struct hvf_sreg_match {
#undef DEF_SYSREG
-#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) { HVF_ID },
+#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID,
-static struct hvf_sreg_match hvf_sreg_match[] = {
+static const hv_sys_reg_t hvf_sreg_list[] = {
#include "sysreg.c.inc"
};
@@ -434,7 +429,7 @@ int hvf_get_registers(CPUState *cpu)
hv_return_t ret;
uint64_t val;
hv_simd_fp_uchar16_t fpval;
- int i;
+ int i, n;
for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val);
@@ -463,13 +458,9 @@ int hvf_get_registers(CPUState *cpu)
assert_hvf_ok(ret);
pstate_write(env, val);
- for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
- int hvf_id = hvf_sreg_match[i].reg;
- uint64_t kvm_id = HVF_TO_KVMID(hvf_id);
-
- if (hvf_sreg_match[i].cp_idx == -1) {
- continue;
- }
+ for (i = 0, n = arm_cpu->cpreg_array_len; i < n; i++) {
+ uint64_t kvm_id = arm_cpu->cpreg_indexes[i];
+ int hvf_id = KVMID_TO_HVF(kvm_id);
if (cpu->accel->guest_debug_enabled) {
/* Handle debug registers */
@@ -553,7 +544,7 @@ int hvf_get_registers(CPUState *cpu)
val = read_raw_cp_reg(env, ri);
- arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
+ arm_cpu->cpreg_values[i] = val;
continue;
}
}
@@ -562,7 +553,7 @@ int hvf_get_registers(CPUState *cpu)
ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_id, &val);
assert_hvf_ok(ret);
- arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
+ arm_cpu->cpreg_values[i] = val;
}
assert(write_list_to_cpustate(arm_cpu));
@@ -578,7 +569,7 @@ int hvf_put_registers(CPUState *cpu)
hv_return_t ret;
uint64_t val;
hv_simd_fp_uchar16_t fpval;
- int i;
+ int i, n;
for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);
@@ -605,12 +596,9 @@ int hvf_put_registers(CPUState *cpu)
aarch64_save_sp(env, arm_current_el(env));
assert(write_cpustate_to_list(arm_cpu, false));
- for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
- int hvf_id = hvf_sreg_match[i].reg;
-
- if (hvf_sreg_match[i].cp_idx == -1) {
- continue;
- }
+ for (i = 0, n = arm_cpu->cpreg_array_len; i < n; i++) {
+ uint64_t kvm_id = arm_cpu->cpreg_indexes[i];
+ int hvf_id = KVMID_TO_HVF(kvm_id);
if (cpu->accel->guest_debug_enabled) {
/* Handle debug registers */
@@ -688,7 +676,7 @@ int hvf_put_registers(CPUState *cpu)
}
}
- val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
+ val = arm_cpu->cpreg_values[i];
ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_id, val);
assert_hvf_ok(ret);
}
@@ -899,7 +887,7 @@ int hvf_arch_init_vcpu(CPUState *cpu)
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
CPUARMState *env = &arm_cpu->env;
- uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match);
+ uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_list);
uint32_t sregs_cnt = 0;
uint64_t pfr;
hv_return_t ret;
@@ -924,17 +912,14 @@ int hvf_arch_init_vcpu(CPUState *cpu)
/* Populate cp list for all known sysregs */
for (i = 0; i < sregs_match_len; i++) {
- int hvf_id = hvf_sreg_match[i].reg;
+ hv_sys_reg_t hvf_id = hvf_sreg_list[i];
uint64_t kvm_id = HVF_TO_KVMID(hvf_id);
uint32_t key = kvm_to_cpreg_id(kvm_id);
const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
if (ri) {
assert(!(ri->type & ARM_CP_NO_RAW));
- hvf_sreg_match[i].cp_idx = sregs_cnt;
arm_cpu->cpreg_indexes[sregs_cnt++] = kvm_id;
- } else {
- hvf_sreg_match[i].cp_idx = -1;
}
}
arm_cpu->cpreg_array_len = sregs_cnt;
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 10/44] target/arm/hvf: Sort the cpreg_indexes array
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2025-09-26 14:08 ` [PULL 09/44] target/arm/hvf: Replace hvf_sreg_match with hvf_sreg_list Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 11/44] target/arm/hvf: Use raw_read, raw_write to access Peter Maydell
` (34 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/hvf/hvf.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index b043eac8c62..99d8672b9bc 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -925,6 +925,9 @@ int hvf_arch_init_vcpu(CPUState *cpu)
arm_cpu->cpreg_array_len = sregs_cnt;
arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
+ /* cpreg tuples must be in strictly ascending order */
+ qsort(arm_cpu->cpreg_indexes, sregs_cnt, sizeof(uint64_t), compare_u64);
+
assert(write_cpustate_to_list(arm_cpu, false));
/* Set CP_NO_RAW system registers on init */
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 11/44] target/arm/hvf: Use raw_read, raw_write to access
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2025-09-26 14:08 ` [PULL 10/44] target/arm/hvf: Sort the cpreg_indexes array Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 12/44] target/arm: Use raw_write in cp_reg_reset Peter Maydell
` (33 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reduce the places that know about field types by 2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/hvf/hvf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 99d8672b9bc..694584cc130 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1153,7 +1153,7 @@ static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
} else if (ri->readfn) {
*val = ri->readfn(env, ri);
} else {
- *val = CPREG_FIELD64(env, ri);
+ *val = raw_read(env, ri);
}
trace_hvf_vgic_read(ri->name, *val);
return true;
@@ -1435,7 +1435,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
if (ri->writefn) {
ri->writefn(env, ri, val);
} else {
- CPREG_FIELD64(env, ri) = val;
+ raw_write(env, ri, val);
}
trace_hvf_vgic_write(ri->name, val);
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 12/44] target/arm: Use raw_write in cp_reg_reset
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2025-09-26 14:08 ` [PULL 11/44] target/arm/hvf: Use raw_read, raw_write to access Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 13/44] target/arm: Rename all ARMCPRegInfo from opaque to ri Peter Maydell
` (32 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reduce the places that know about field types by 1.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c65af7e7614..91ae56dddb2 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -192,14 +192,8 @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
* This is basically only used for fields in non-core coprocessors
* (like the pxa2xx ones).
*/
- if (!ri->fieldoffset) {
- return;
- }
-
- if (cpreg_field_is_64bit(ri)) {
- CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
- } else {
- CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
+ if (ri->fieldoffset) {
+ raw_write(&cpu->env, ri, ri->resetvalue);
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 13/44] target/arm: Rename all ARMCPRegInfo from opaque to ri
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2025-09-26 14:08 ` [PULL 12/44] target/arm: Use raw_write in cp_reg_reset Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 14/44] target/arm: Drop define_one_arm_cp_reg_with_opaque Peter Maydell
` (31 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
These pointers are no opaque, they have a specific type.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 10 +++++-----
target/arm/helper.c | 6 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 2a4826f5c4f..8f3e728d8ed 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -866,15 +866,15 @@ typedef struct ARMCPRegInfo ARMCPRegInfo;
* Access functions for coprocessor registers. These cannot fail and
* may not raise exceptions.
*/
-typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
+typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *ri);
+typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value);
/* Access permission check functions for coprocessor registers. */
typedef CPAccessResult CPAccessFn(CPUARMState *env,
- const ARMCPRegInfo *opaque,
+ const ARMCPRegInfo *ri,
bool isread);
/* Hook function for register reset */
-typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *ri);
#define CP_ANY 0xff
@@ -1100,7 +1100,7 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value);
* CPResetFn that does nothing, for use if no reset is required even
* if fieldoffset is non zero.
*/
-void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
+void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri);
/*
* Return true if this reginfo struct's field in the cpu state struct
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 009f8d6fa1c..7b23e7e5889 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1073,7 +1073,7 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
.resetvalue = 0 },
};
-static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
+static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = env_archcpu(env);
@@ -5382,7 +5382,7 @@ static const ARMCPRegInfo rndr_reginfo[] = {
.access = PL0_R, .readfn = rndr_readfn },
};
-static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
+static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
#ifdef CONFIG_TCG
@@ -7829,7 +7829,7 @@ uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
return 0;
}
-void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
+void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Helper coprocessor reset function for do-nothing-on-reset registers */
}
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 14/44] target/arm: Drop define_one_arm_cp_reg_with_opaque
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2025-09-26 14:08 ` [PULL 13/44] target/arm: Rename all ARMCPRegInfo from opaque to ri Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 15/44] target/arm: Restrict the scope of CPREG_FIELD32, CPREG_FIELD64 Peter Maydell
` (30 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
The last use of this interface was removed in 603bc048a27f
("hw/arm: Remove pxa2xx_pic"). As the comment in gicv3
stated, keeping pointer references to cpregs has SMP issues,
so avoid future temptation by removing the interface.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 32 ++++++++------------------------
hw/intc/arm_gicv3_cpuif.c | 10 +---------
target/arm/helper.c | 29 +++++++++++------------------
3 files changed, 20 insertions(+), 51 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 8f3e728d8ed..d02d74f1f5d 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -931,11 +931,7 @@ struct ARMCPRegInfo {
*/
uint32_t nv2_redirect_offset;
- /*
- * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
- * this register was defined: can be used to hand data through to the
- * register read/write functions, since they are passed the ARMCPRegInfo*.
- */
+ /* This is used only by VHE. */
void *opaque;
/*
* Value of this register, if it is ARM_CP_CONST. Otherwise, if
@@ -1029,27 +1025,15 @@ struct ARMCPRegInfo {
#define CPREG_FIELD64(env, ri) \
(*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
- void *opaque);
+void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs);
+void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t len);
-static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
- define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
-}
-
-void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
- void *opaque, size_t len);
-
-#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \
- do { \
- QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
- define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \
- ARRAY_SIZE(REGS)); \
+#define define_arm_cp_regs(CPU, REGS) \
+ do { \
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
+ define_arm_cp_regs_len(CPU, REGS, ARRAY_SIZE(REGS)); \
} while (0)
-#define define_arm_cp_regs(CPU, REGS) \
- define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
-
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
/*
@@ -1168,7 +1152,7 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri)
* means that the right set of registers is exactly those where
* the opc1 field is 4 or 5. (You can see this also in the assert
* we do that the opc1 field and the permissions mask line up in
- * define_one_arm_cp_reg_with_opaque().)
+ * define_one_arm_cp_reg().)
* Checking the opc1 field is easier for us and avoids the problem
* that we do not consistently use the right architectural names
* for all sysregs, since we treat the name field as largely for debug.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 4b4cf091570..72e91f971a4 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -3037,15 +3037,7 @@ void gicv3_init_cpuif(GICv3State *s)
* cpu->gic_pribits
*/
- /* Note that we can't just use the GICv3CPUState as an opaque pointer
- * in define_arm_cp_regs_with_opaque(), because when we're called back
- * it might be with code translated by CPU 0 but run by CPU 1, in
- * which case we'd get the wrong value.
- * So instead we define the regs with no ri->opaque info, and
- * get back to the GICv3CPUState from the CPUARMState.
- *
- * These CP regs callbacks can be called from either TCG or HVF code.
- */
+ /* These CP regs callbacks can be called from either TCG or HVF. */
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
/*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7b23e7e5889..b76a0edb0f4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7355,12 +7355,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
/*
- * Private utility function for define_one_arm_cp_reg_with_opaque():
+ * Private utility function for define_one_arm_cp_reg():
* add a single reginfo struct to the hash table.
*/
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
- void *opaque, CPState state,
- CPSecureState secstate,
+ CPState state, CPSecureState secstate,
int crm, int opc1, int opc2,
const char *name)
{
@@ -7448,9 +7447,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
r2->opc2 = opc2;
r2->state = state;
r2->secure = secstate;
- if (opaque) {
- r2->opaque = opaque;
- }
if (make_const) {
/* This should not have been a very special register to begin. */
@@ -7555,8 +7551,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
}
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
- const ARMCPRegInfo *r, void *opaque)
+void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
{
/*
* Define implementations of coprocessor registers.
@@ -7715,7 +7710,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
if (nxs_ri.fgt) {
nxs_ri.fgt |= R_FGT_NXS_MASK;
}
- add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state,
+ add_cpreg_to_hashtable(cpu, &nxs_ri, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2, name);
}
@@ -7729,17 +7724,17 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
switch (r->secure) {
case ARM_CP_SECSTATE_S:
case ARM_CP_SECSTATE_NS:
- add_cpreg_to_hashtable(cpu, r, opaque, state,
+ add_cpreg_to_hashtable(cpu, r, state,
r->secure, crm, opc1, opc2,
r->name);
break;
case ARM_CP_SECSTATE_BOTH:
name = g_strdup_printf("%s_S", r->name);
- add_cpreg_to_hashtable(cpu, r, opaque, state,
+ add_cpreg_to_hashtable(cpu, r, state,
ARM_CP_SECSTATE_S,
crm, opc1, opc2, name);
g_free(name);
- add_cpreg_to_hashtable(cpu, r, opaque, state,
+ add_cpreg_to_hashtable(cpu, r, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2, r->name);
break;
@@ -7751,7 +7746,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
* AArch64 registers get mapped to non-secure instance
* of AArch32
*/
- add_cpreg_to_hashtable(cpu, r, opaque, state,
+ add_cpreg_to_hashtable(cpu, r, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2, r->name);
}
@@ -7762,12 +7757,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
}
/* Define a whole list of registers */
-void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
- void *opaque, size_t len)
+void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t len)
{
- size_t i;
- for (i = 0; i < len; ++i) {
- define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque);
+ for (size_t i = 0; i < len; ++i) {
+ define_one_arm_cp_reg(cpu, regs + i);
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 15/44] target/arm: Restrict the scope of CPREG_FIELD32, CPREG_FIELD64
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2025-09-26 14:08 ` [PULL 14/44] target/arm: Drop define_one_arm_cp_reg_with_opaque Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 16/44] target/arm: Replace cpreg_field_is_64bit with cpreg_field_type Peter Maydell
` (29 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 9 ---------
target/arm/helper.c | 12 ++++++++++++
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index d02d74f1f5d..6fb1994afa0 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1016,15 +1016,6 @@ struct ARMCPRegInfo {
CPAccessFn *orig_accessfn;
};
-/*
- * Macros which are lvalues for the field in CPUARMState for the
- * ARMCPRegInfo *ri.
- */
-#define CPREG_FIELD32(env, ri) \
- (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
-#define CPREG_FIELD64(env, ri) \
- (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
-
void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs);
void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t len);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b76a0edb0f4..fe298670f12 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -51,6 +51,15 @@ int compare_u64(const void *a, const void *b)
return 0;
}
+/*
+ * Macros which are lvalues for the field in CPUARMState for the
+ * ARMCPRegInfo *ri.
+ */
+#define CPREG_FIELD32(env, ri) \
+ (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
+#define CPREG_FIELD64(env, ri) \
+ (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
+
uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
assert(ri->fieldoffset);
@@ -71,6 +80,9 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
}
}
+#undef CPREG_FIELD32
+#undef CPREG_FIELD64
+
static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
{
return (char *)env + ri->fieldoffset;
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 16/44] target/arm: Replace cpreg_field_is_64bit with cpreg_field_type
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2025-09-26 14:08 ` [PULL 15/44] target/arm: Restrict the scope of CPREG_FIELD32, CPREG_FIELD64 Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 17/44] target/arm: Add CP_REG_AA32_64BIT_{SHIFT,MASK} Peter Maydell
` (28 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Prepare for 128-bit fields by using a better query api.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 10 ++++++----
target/arm/gdbstub.c | 7 +++++--
target/arm/helper.c | 18 +++++++++++++-----
3 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 6fb1994afa0..74bae7309a3 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -22,6 +22,7 @@
#define TARGET_ARM_CPREGS_H
#include "hw/registerfields.h"
+#include "exec/memop.h"
#include "target/arm/kvm-consts.h"
#include "cpu.h"
@@ -1078,12 +1079,13 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value);
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri);
/*
- * Return true if this reginfo struct's field in the cpu state struct
- * is 64 bits wide.
+ * Return MO_32 if the field in CPUARMState is uint32_t or
+ * MO_64 if the field in CPUARMState is uint64_t.
*/
-static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
+static inline MemOp cpreg_field_type(const ARMCPRegInfo *ri)
{
- return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
+ return (ri->state == ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT)
+ ? MO_64 : MO_32);
}
static inline bool cp_access_ok(int current_el,
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 2d331fff445..4e2ac49b6a9 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -247,10 +247,13 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg)
key = cpu->dyn_sysreg_feature.data.cpregs.keys[reg];
ri = get_arm_cp_reginfo(cpu->cp_regs, key);
if (ri) {
- if (cpreg_field_is_64bit(ri)) {
+ switch (cpreg_field_type(ri)) {
+ case MO_64:
return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
- } else {
+ case MO_32:
return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
+ default:
+ g_assert_not_reached();
}
}
return 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index fe298670f12..26941ecd4f8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -63,20 +63,28 @@ int compare_u64(const void *a, const void *b)
uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
assert(ri->fieldoffset);
- if (cpreg_field_is_64bit(ri)) {
+ switch (cpreg_field_type(ri)) {
+ case MO_64:
return CPREG_FIELD64(env, ri);
- } else {
+ case MO_32:
return CPREG_FIELD32(env, ri);
+ default:
+ g_assert_not_reached();
}
}
void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
assert(ri->fieldoffset);
- if (cpreg_field_is_64bit(ri)) {
+ switch (cpreg_field_type(ri)) {
+ case MO_64:
CPREG_FIELD64(env, ri) = value;
- } else {
+ break;
+ case MO_32:
CPREG_FIELD32(env, ri) = value;
+ break;
+ default:
+ g_assert_not_reached();
}
}
@@ -2754,7 +2762,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* If the ASID changes (with a 64-bit write), we must flush the TLB. */
- if (cpreg_field_is_64bit(ri) &&
+ if (cpreg_field_type(ri) == MO_64 &&
extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
ARMCPU *cpu = env_archcpu(env);
tlb_flush(CPU(cpu));
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 17/44] target/arm: Add CP_REG_AA32_64BIT_{SHIFT,MASK}
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2025-09-26 14:08 ` [PULL 16/44] target/arm: Replace cpreg_field_is_64bit with cpreg_field_type Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 18/44] target/arm: Rename CP_REG_AA32_NS_{SHIFT,MASK} Peter Maydell
` (27 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Give a name to the bit we're already using.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 74bae7309a3..f7dd6d2f758 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -178,9 +178,14 @@ enum {
#define CP_REG_NS_SHIFT 29
#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
+/* Distinguish 32-bit and 64-bit views of AArch32 system registers. */
+#define CP_REG_AA32_64BIT_SHIFT 15
+#define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT)
+
#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
- ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
- ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
+ (((ns) << CP_REG_NS_SHIFT) | \
+ ((is64) << CP_REG_AA32_64BIT_SHIFT) | \
+ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
(CP_REG_AA64_MASK | \
@@ -202,7 +207,7 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
cpregid |= CP_REG_AA64_MASK;
} else {
if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
- cpregid |= (1 << 15);
+ cpregid |= CP_REG_AA32_64BIT_MASK;
}
/*
@@ -226,8 +231,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
kvmid = cpregid & ~CP_REG_AA64_MASK;
kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
} else {
- kvmid = cpregid & ~(1 << 15);
- if (cpregid & (1 << 15)) {
+ kvmid = cpregid & ~CP_REG_AA32_64BIT_MASK;
+ if (cpregid & CP_REG_AA32_64BIT_MASK) {
kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
} else {
kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 18/44] target/arm: Rename CP_REG_AA32_NS_{SHIFT,MASK}
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2025-09-26 14:08 ` [PULL 17/44] target/arm: Add CP_REG_AA32_64BIT_{SHIFT,MASK} Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 19/44] target/arm: Convert init_cpreg_list to g_hash_table_foreach Peter Maydell
` (26 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Rename from CP_REG_NS_* to emphasize this is specific to AArch32.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index f7dd6d2f758..417d79f7ba6 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -175,15 +175,15 @@ enum {
* add a bit to distinguish between secure and non-secure cpregs in the
* hashtable.
*/
-#define CP_REG_NS_SHIFT 29
-#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
+#define CP_REG_AA32_NS_SHIFT 29
+#define CP_REG_AA32_NS_MASK (1 << CP_REG_AA32_NS_SHIFT)
/* Distinguish 32-bit and 64-bit views of AArch32 system registers. */
#define CP_REG_AA32_64BIT_SHIFT 15
#define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT)
#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
- (((ns) << CP_REG_NS_SHIFT) | \
+ (((ns) << CP_REG_AA32_NS_SHIFT) | \
((is64) << CP_REG_AA32_64BIT_SHIFT) | \
((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
@@ -214,7 +214,7 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
* KVM is always non-secure so add the NS flag on AArch32 register
* entries.
*/
- cpregid |= 1 << CP_REG_NS_SHIFT;
+ cpregid |= CP_REG_AA32_NS_MASK;
}
return cpregid;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 19/44] target/arm: Convert init_cpreg_list to g_hash_table_foreach
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2025-09-26 14:08 ` [PULL 18/44] target/arm: Rename CP_REG_AA32_NS_{SHIFT,MASK} Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 20/44] target/arm: Remove cp argument to ENCODE_AA64_CP_REG Peter Maydell
` (25 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Adjust count_cpreg and add_cpreg_to_list to be used with
g_hash_table_foreach instead of g_list_foreach. In this way we have
the ARMCPRegInfo pointer directly rather than having to look it up
from the key.
Delay the sorting of the cpreg_indexes until after add_cpreg_to_list.
This allows us to sort the data that we actually care about,
the kvm id, as computed within add_cpreg_to_list, instead of
having to repeatedly compute the kvm id within cpreg_key_compare.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 54 ++++++++++++++++++---------------------------
1 file changed, 21 insertions(+), 33 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 26941ecd4f8..27d5ab82920 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -229,11 +229,11 @@ bool write_list_to_cpustate(ARMCPU *cpu)
return ok;
}
-static void add_cpreg_to_list(gpointer key, gpointer opaque)
+static void add_cpreg_to_list(gpointer key, gpointer value, gpointer opaque)
{
ARMCPU *cpu = opaque;
uint32_t regidx = (uintptr_t)key;
- const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+ const ARMCPRegInfo *ri = value;
if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
@@ -242,61 +242,49 @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
}
}
-static void count_cpreg(gpointer key, gpointer opaque)
+static void count_cpreg(gpointer key, gpointer value, gpointer opaque)
{
ARMCPU *cpu = opaque;
- const ARMCPRegInfo *ri;
-
- ri = g_hash_table_lookup(cpu->cp_regs, key);
+ const ARMCPRegInfo *ri = value;
if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
cpu->cpreg_array_len++;
}
}
-static gint cpreg_key_compare(gconstpointer a, gconstpointer b, gpointer d)
-{
- uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a);
- uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b);
-
- if (aidx > bidx) {
- return 1;
- }
- if (aidx < bidx) {
- return -1;
- }
- return 0;
-}
-
void init_cpreg_list(ARMCPU *cpu)
{
/*
* Initialise the cpreg_tuples[] array based on the cp_regs hash.
* Note that we require cpreg_tuples[] to be sorted by key ID.
*/
- GList *keys;
int arraylen;
- keys = g_hash_table_get_keys(cpu->cp_regs);
- keys = g_list_sort_with_data(keys, cpreg_key_compare, NULL);
-
cpu->cpreg_array_len = 0;
-
- g_list_foreach(keys, count_cpreg, cpu);
+ g_hash_table_foreach(cpu->cp_regs, count_cpreg, cpu);
arraylen = cpu->cpreg_array_len;
- cpu->cpreg_indexes = g_new(uint64_t, arraylen);
- cpu->cpreg_values = g_new(uint64_t, arraylen);
- cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
- cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
- cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
+ if (arraylen) {
+ cpu->cpreg_indexes = g_new(uint64_t, arraylen);
+ cpu->cpreg_values = g_new(uint64_t, arraylen);
+ cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
+ cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
+ } else {
+ cpu->cpreg_indexes = NULL;
+ cpu->cpreg_values = NULL;
+ cpu->cpreg_vmstate_indexes = NULL;
+ cpu->cpreg_vmstate_values = NULL;
+ }
+ cpu->cpreg_vmstate_array_len = arraylen;
cpu->cpreg_array_len = 0;
- g_list_foreach(keys, add_cpreg_to_list, cpu);
+ g_hash_table_foreach(cpu->cp_regs, add_cpreg_to_list, cpu);
assert(cpu->cpreg_array_len == arraylen);
- g_list_free(keys);
+ if (arraylen) {
+ qsort(cpu->cpreg_indexes, arraylen, sizeof(uint64_t), compare_u64);
+ }
}
bool arm_pan_enabled(CPUARMState *env)
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 20/44] target/arm: Remove cp argument to ENCODE_AA64_CP_REG
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2025-09-26 14:08 ` [PULL 19/44] target/arm: Convert init_cpreg_list to g_hash_table_foreach Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 21/44] target/arm: Reorder ENCODE_AA64_CP_REG arguments Peter Maydell
` (24 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
All invocations were required to pass the same value,
CP_REG_ARM64_SYSREG_CP. Bake that in to the result directly.
Remove CP_REG_ARM64_SYSREG_CP as unused.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 5 ++---
target/arm/kvm-consts.h | 3 ---
target/arm/helper.c | 11 +++++------
target/arm/hvf/hvf.c | 3 +--
target/arm/tcg/translate-a64.c | 6 ++----
5 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 417d79f7ba6..a10abadb932 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -187,9 +187,8 @@ enum {
((is64) << CP_REG_AA32_64BIT_SHIFT) | \
((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
-#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
- (CP_REG_AA64_MASK | \
- ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
+#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \
+ (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \
((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index fdb305eea1a..54ae5da7ce3 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -160,9 +160,6 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53);
#define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
#define CP_REG_ARM64_SYSREG_OP2_SHIFT 0
-/* No kernel define but it's useful to QEMU */
-#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT)
-
MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64);
MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK);
MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 27d5ab82920..2732112ff21 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4503,7 +4503,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
};
#define K(op0, op1, crn, crm, op2) \
- ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
+ ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2)
static const struct E2HAlias aliases[] = {
{ K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
@@ -7396,10 +7396,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
* in their AArch64 view (the .cp value may be non-zero for the
* benefit of the AArch32 view).
*/
- if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
- cp = CP_REG_ARM64_SYSREG_CP;
- }
- key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
+ assert(cp == 0 || r->state == ARM_CP_STATE_BOTH);
+ cp = 0;
+ key = ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2);
break;
default:
g_assert_not_reached();
@@ -7624,7 +7623,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
}
break;
case ARM_CP_STATE_AA64:
- assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP);
+ assert(r->cp == 0);
break;
default:
g_assert_not_reached();
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 694584cc130..6e67d89163f 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1124,8 +1124,7 @@ static bool is_id_sysreg(uint32_t reg)
static uint32_t hvf_reg2cp_reg(uint32_t reg)
{
- return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
- (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
+ return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
(reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
(reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
(reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 37bedc3780b..a560ef0f42c 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -2466,8 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread,
unsigned int op0, unsigned int op1, unsigned int op2,
unsigned int crn, unsigned int crm, unsigned int rt)
{
- uint32_t key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
- crn, crm, op0, op1, op2);
+ uint32_t key = ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2);
const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
bool need_exit_tb = false;
bool nv_trap_to_el2 = false;
@@ -2603,8 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread,
* We don't use the EL1 register's access function, and
* fine-grained-traps on EL1 also do not apply here.
*/
- key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
- crn, crm, op0, 0, op2);
+ key = ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2);
ri = get_arm_cp_reginfo(s->cp_regs, key);
assert(ri);
assert(cp_access_ok(s->current_el, ri, isread));
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 21/44] target/arm: Reorder ENCODE_AA64_CP_REG arguments
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2025-09-26 14:08 ` [PULL 20/44] target/arm: Remove cp argument to ENCODE_AA64_CP_REG Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 22/44] target/arm: Split out add_cpreg_to_hashtable_aa{32, 64} Peter Maydell
` (23 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
The order of the parameters in the Arm ARM is
op0, op1, crn, crm, op2
Reorder the arguments of ENCODE_AA64_CP_REG to match.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 2 +-
target/arm/helper.c | 4 ++--
target/arm/hvf/hvf.c | 6 +++---
target/arm/tcg/translate-a64.c | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index a10abadb932..08fc42ea571 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -187,7 +187,7 @@ enum {
((is64) << CP_REG_AA32_64BIT_SHIFT) | \
((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
-#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \
+#define ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) \
(CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \
((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2732112ff21..965941f04e5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4503,7 +4503,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
};
#define K(op0, op1, crn, crm, op2) \
- ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2)
+ ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2)
static const struct E2HAlias aliases[] = {
{ K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
@@ -7398,7 +7398,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
*/
assert(cp == 0 || r->state == ARM_CP_STATE_BOTH);
cp = 0;
- key = ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2);
+ key = ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2);
break;
default:
g_assert_not_reached();
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 6e67d89163f..8b467b36638 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1124,10 +1124,10 @@ static bool is_id_sysreg(uint32_t reg)
static uint32_t hvf_reg2cp_reg(uint32_t reg)
{
- return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
- (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
- (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
+ return ENCODE_AA64_CP_REG((reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
(reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
+ (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
+ (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
(reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
}
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index a560ef0f42c..0ec309f1ea9 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -2466,7 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread,
unsigned int op0, unsigned int op1, unsigned int op2,
unsigned int crn, unsigned int crm, unsigned int rt)
{
- uint32_t key = ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2);
+ uint32_t key = ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2);
const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
bool need_exit_tb = false;
bool nv_trap_to_el2 = false;
@@ -2602,7 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread,
* We don't use the EL1 register's access function, and
* fine-grained-traps on EL1 also do not apply here.
*/
- key = ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2);
+ key = ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2);
ri = get_arm_cp_reginfo(s->cp_regs, key);
assert(ri);
assert(cp_access_ok(s->current_el, ri, isread));
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 22/44] target/arm: Split out add_cpreg_to_hashtable_aa{32, 64}
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2025-09-26 14:08 ` [PULL 21/44] target/arm: Reorder ENCODE_AA64_CP_REG arguments Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 23/44] target/arm: Improve asserts in define_one_arm_cp_reg Peter Maydell
` (22 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
The nesting level for the inner loop of define_one_arm_cp_reg
was overly deep. Split out that code into two functions, for
the AArch32 and AArch64 paths separately. Simplify the innermost
loop to a switch statement over r->state.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 147 +++++++++++++++++++++++---------------------
1 file changed, 76 insertions(+), 71 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 965941f04e5..39f5297a1a7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7557,6 +7557,66 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
}
+static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r,
+ int crm, int opc1, int opc2)
+{
+ /*
+ * Under AArch32 CP registers can be common
+ * (same for secure and non-secure world) or banked.
+ */
+ char *name;
+
+ assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */
+
+ switch (r->secure) {
+ case ARM_CP_SECSTATE_S:
+ case ARM_CP_SECSTATE_NS:
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
+ r->secure, crm, opc1, opc2, r->name);
+ break;
+ case ARM_CP_SECSTATE_BOTH:
+ name = g_strdup_printf("%s_S", r->name);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
+ ARM_CP_SECSTATE_S, crm, opc1, opc2, name);
+ g_free(name);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
+ ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r,
+ int crm, int opc1, int opc2)
+{
+ if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
+ cpu_isar_feature(aa64_xs, cpu)) {
+ /*
+ * This is a TLBI insn which has an NXS variant. The
+ * NXS variant is at the same encoding except that
+ * crn is +1, and has the same behaviour except for
+ * fine-grained trapping. Add the NXS insn here and
+ * then fall through to add the normal register.
+ * add_cpreg_to_hashtable() copies the cpreg struct
+ * and name that it is passed, so it's OK to use
+ * a local struct here.
+ */
+ ARMCPRegInfo nxs_ri = *r;
+ g_autofree char *name = g_strdup_printf("%sNXS", r->name);
+
+ assert(nxs_ri.crn < 0xf);
+ nxs_ri.crn++;
+ if (nxs_ri.fgt) {
+ nxs_ri.fgt |= R_FGT_NXS_MASK;
+ }
+ add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64,
+ ARM_CP_SECSTATE_NS, crm, opc1, opc2, name);
+ }
+
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS,
+ crm, opc1, opc2, r->name);
+}
void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
{
@@ -7584,14 +7644,12 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
* the register, if any.
*/
- int crm, opc1, opc2;
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
- CPState state;
/* 64 bit registers have only CRm and Opc1 fields */
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
@@ -7688,75 +7746,22 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
}
}
- for (crm = crmmin; crm <= crmmax; crm++) {
- for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
- for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
- for (state = ARM_CP_STATE_AA32;
- state <= ARM_CP_STATE_AA64; state++) {
- if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
- continue;
- }
- if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
- cpu_isar_feature(aa64_xs, cpu)) {
- /*
- * This is a TLBI insn which has an NXS variant. The
- * NXS variant is at the same encoding except that
- * crn is +1, and has the same behaviour except for
- * fine-grained trapping. Add the NXS insn here and
- * then fall through to add the normal register.
- * add_cpreg_to_hashtable() copies the cpreg struct
- * and name that it is passed, so it's OK to use
- * a local struct here.
- */
- ARMCPRegInfo nxs_ri = *r;
- g_autofree char *name = g_strdup_printf("%sNXS", r->name);
-
- assert(state == ARM_CP_STATE_AA64);
- assert(nxs_ri.crn < 0xf);
- nxs_ri.crn++;
- if (nxs_ri.fgt) {
- nxs_ri.fgt |= R_FGT_NXS_MASK;
- }
- add_cpreg_to_hashtable(cpu, &nxs_ri, state,
- ARM_CP_SECSTATE_NS,
- crm, opc1, opc2, name);
- }
- if (state == ARM_CP_STATE_AA32) {
- /*
- * Under AArch32 CP registers can be common
- * (same for secure and non-secure world) or banked.
- */
- char *name;
-
- switch (r->secure) {
- case ARM_CP_SECSTATE_S:
- case ARM_CP_SECSTATE_NS:
- add_cpreg_to_hashtable(cpu, r, state,
- r->secure, crm, opc1, opc2,
- r->name);
- break;
- case ARM_CP_SECSTATE_BOTH:
- name = g_strdup_printf("%s_S", r->name);
- add_cpreg_to_hashtable(cpu, r, state,
- ARM_CP_SECSTATE_S,
- crm, opc1, opc2, name);
- g_free(name);
- add_cpreg_to_hashtable(cpu, r, state,
- ARM_CP_SECSTATE_NS,
- crm, opc1, opc2, r->name);
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- /*
- * AArch64 registers get mapped to non-secure instance
- * of AArch32
- */
- add_cpreg_to_hashtable(cpu, r, state,
- ARM_CP_SECSTATE_NS,
- crm, opc1, opc2, r->name);
- }
+ for (int crm = crmmin; crm <= crmmax; crm++) {
+ for (int opc1 = opc1min; opc1 <= opc1max; opc1++) {
+ for (int opc2 = opc2min; opc2 <= opc2max; opc2++) {
+ switch (r->state) {
+ case ARM_CP_STATE_AA32:
+ add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2);
+ break;
+ case ARM_CP_STATE_AA64:
+ add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2);
+ break;
+ case ARM_CP_STATE_BOTH:
+ add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2);
+ break;
+ default:
+ g_assert_not_reached();
}
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 23/44] target/arm: Improve asserts in define_one_arm_cp_reg
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2025-09-26 14:08 ` [PULL 22/44] target/arm: Split out add_cpreg_to_hashtable_aa{32, 64} Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 24/44] target/arm: Move cp processing to define_one_arm_cp_reg Peter Maydell
` (21 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reject ARM_CP_64BIT with ARM_CP_STATE_BOTH, because encoding
constrains prevent it from working. Remove some extra parens;
distribute ! across && to simplify.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 39f5297a1a7..8c2b7e037e8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7651,12 +7651,17 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
- /* 64 bit registers have only CRm and Opc1 fields */
- assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
+ /*
+ * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless.
+ * Moreover, the encoding test just following in general prevents
+ * shared encoding so ARM_CP_STATE_BOTH won't work either.
+ */
+ assert(r->state == ARM_CP_STATE_AA32 || !(r->type & ARM_CP_64BIT));
+ /* AArch32 64-bit registers have only CRm and Opc1 fields. */
+ assert(!(r->type & ARM_CP_64BIT) || !(r->opc2 || r->crn));
/* op0 only exists in the AArch64 encodings */
- assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
- /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
- assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
+ assert(r->state != ARM_CP_STATE_AA32 || r->opc0 == 0);
+
/*
* This API is only for Arm's system coprocessors (14 and 15) or
* (M-profile or v7A-and-earlier only) for implementation defined
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 24/44] target/arm: Move cp processing to define_one_arm_cp_reg
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2025-09-26 14:08 ` [PULL 23/44] target/arm: Improve asserts in define_one_arm_cp_reg Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 25/44] target/arm: Move cpreg elimination " Peter Maydell
` (20 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Processing of cp was split between add_cpreg_to_hashtable and
define_one_arm_cp_reg. Unify it all to the top-level function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 53 +++++++++++++++++++--------------------------
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8c2b7e037e8..f0e423e623b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7368,7 +7368,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
*/
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
CPState state, CPSecureState secstate,
- int crm, int opc1, int opc2,
+ int cp, int crm, int opc1, int opc2,
const char *name)
{
CPUARMState *env = &cpu->env;
@@ -7376,28 +7376,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
ARMCPRegInfo *r2;
bool is64 = r->type & ARM_CP_64BIT;
bool ns = secstate & ARM_CP_SECSTATE_NS;
- int cp = r->cp;
size_t name_len;
bool make_const;
switch (state) {
case ARM_CP_STATE_AA32:
- /* We assume it is a cp15 register if the .cp field is left unset. */
- if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
- cp = 15;
- }
key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
break;
case ARM_CP_STATE_AA64:
- /*
- * To allow abbreviation of ARMCPRegInfo definitions, we treat
- * cp == 0 as equivalent to the value for "standard guest-visible
- * sysreg". STATE_BOTH definitions are also always "standard sysreg"
- * in their AArch64 view (the .cp value may be non-zero for the
- * benefit of the AArch32 view).
- */
- assert(cp == 0 || r->state == ARM_CP_STATE_BOTH);
- cp = 0;
key = ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2);
break;
default:
@@ -7558,7 +7544,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
}
static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r,
- int crm, int opc1, int opc2)
+ int cp, int crm, int opc1, int opc2)
{
/*
* Under AArch32 CP registers can be common
@@ -7571,16 +7557,16 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r,
switch (r->secure) {
case ARM_CP_SECSTATE_S:
case ARM_CP_SECSTATE_NS:
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
- r->secure, crm, opc1, opc2, r->name);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure,
+ cp, crm, opc1, opc2, r->name);
break;
case ARM_CP_SECSTATE_BOTH:
name = g_strdup_printf("%s_S", r->name);
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
- ARM_CP_SECSTATE_S, crm, opc1, opc2, name);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_S,
+ cp, crm, opc1, opc2, name);
g_free(name);
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
- ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_NS,
+ cp, crm, opc1, opc2, r->name);
break;
default:
g_assert_not_reached();
@@ -7611,11 +7597,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r,
nxs_ri.fgt |= R_FGT_NXS_MASK;
}
add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64,
- ARM_CP_SECSTATE_NS, crm, opc1, opc2, name);
+ ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, name);
}
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS,
- crm, opc1, opc2, r->name);
+ 0, crm, opc1, opc2, r->name);
}
void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
@@ -7650,6 +7636,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
+ int cp = r->cp;
/*
* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless.
@@ -7672,21 +7659,25 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
*/
switch (r->state) {
case ARM_CP_STATE_BOTH:
- /* 0 has a special meaning, but otherwise the same rules as AA32. */
- if (r->cp == 0) {
+ /*
+ * If the cp field is left unset, assume cp15.
+ * Otherwise apply the same rules as AA32.
+ */
+ if (cp == 0) {
+ cp = 15;
break;
}
/* fall through */
case ARM_CP_STATE_AA32:
if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
!arm_feature(&cpu->env, ARM_FEATURE_M)) {
- assert(r->cp >= 14 && r->cp <= 15);
+ assert(cp >= 14 && cp <= 15);
} else {
- assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15));
+ assert(cp < 8 || (cp >= 14 && cp <= 15));
}
break;
case ARM_CP_STATE_AA64:
- assert(r->cp == 0);
+ assert(cp == 0);
break;
default:
g_assert_not_reached();
@@ -7756,13 +7747,13 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
for (int opc2 = opc2min; opc2 <= opc2max; opc2++) {
switch (r->state) {
case ARM_CP_STATE_AA32:
- add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc2);
break;
case ARM_CP_STATE_AA64:
add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2);
break;
case ARM_CP_STATE_BOTH:
- add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc2);
add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2);
break;
default:
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 25/44] target/arm: Move cpreg elimination to define_one_arm_cp_reg
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2025-09-26 14:08 ` [PULL 24/44] target/arm: Move cp processing to define_one_arm_cp_reg Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 26/44] target/arm: Add key parameter to add_cpreg_to_hashtable Peter Maydell
` (19 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Eliminate unused registers earlier, so that by the time we
arrive in add_cpreg_to_hashtable we never skip.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 123 +++++++++++++++++++++++---------------------
1 file changed, 64 insertions(+), 59 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f0e423e623b..ade16138e75 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7377,7 +7377,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
bool is64 = r->type & ARM_CP_64BIT;
bool ns = secstate & ARM_CP_SECSTATE_NS;
size_t name_len;
- bool make_const;
switch (state) {
case ARM_CP_STATE_AA32:
@@ -7398,32 +7397,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
}
}
- /*
- * Eliminate registers that are not present because the EL is missing.
- * Doing this here makes it easier to put all registers for a given
- * feature into the same ARMCPRegInfo array and define them all at once.
- */
- make_const = false;
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- /*
- * An EL2 register without EL2 but with EL3 is (usually) RES0.
- * See rule RJFFP in section D1.1.3 of DDI0487H.a.
- */
- int min_el = ctz32(r->access) / 2;
- if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
- if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
- return;
- }
- make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
- }
- } else {
- CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
- ? PL2_RW : PL1_RW);
- if ((r->access & max_el) == 0) {
- return;
- }
- }
-
/* Combine cpreg and name into one allocation. */
name_len = strlen(name) + 1;
r2 = g_malloc(sizeof(*r2) + name_len);
@@ -7441,38 +7414,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
r2->state = state;
r2->secure = secstate;
- if (make_const) {
- /* This should not have been a very special register to begin. */
- int old_special = r2->type & ARM_CP_SPECIAL_MASK;
- assert(old_special == 0 || old_special == ARM_CP_NOP);
- /*
- * Set the special function to CONST, retaining the other flags.
- * This is important for e.g. ARM_CP_SVE so that we still
- * take the SVE trap if CPTR_EL3.EZ == 0.
- */
- r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
- /*
- * Usually, these registers become RES0, but there are a few
- * special cases like VPIDR_EL2 which have a constant non-zero
- * value with writes ignored.
- */
- if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
- r2->resetvalue = 0;
- }
- /*
- * ARM_CP_CONST has precedence, so removing the callbacks and
- * offsets are not strictly necessary, but it is potentially
- * less confusing to debug later.
- */
- r2->readfn = NULL;
- r2->writefn = NULL;
- r2->raw_readfn = NULL;
- r2->raw_writefn = NULL;
- r2->resetfn = NULL;
- r2->fieldoffset = 0;
- r2->bank_fieldoffsets[0] = 0;
- r2->bank_fieldoffsets[1] = 0;
- } else {
+ {
bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
if (isbanked) {
@@ -7637,6 +7579,8 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
int cp = r->cp;
+ ARMCPRegInfo r_const;
+ CPUARMState *env = &cpu->env;
/*
* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless.
@@ -7742,6 +7686,67 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
}
}
+ /*
+ * Eliminate registers that are not present because the EL is missing.
+ * Doing this here makes it easier to put all registers for a given
+ * feature into the same ARMCPRegInfo array and define them all at once.
+ */
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ /*
+ * An EL2 register without EL2 but with EL3 is (usually) RES0.
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+ */
+ int min_el = ctz32(r->access) / 2;
+ if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
+ if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
+ return;
+ }
+ if (!(r->type & ARM_CP_EL3_NO_EL2_KEEP)) {
+ /* This should not have been a very special register. */
+ int old_special = r->type & ARM_CP_SPECIAL_MASK;
+ assert(old_special == 0 || old_special == ARM_CP_NOP);
+
+ r_const = *r;
+
+ /*
+ * Set the special function to CONST, retaining the other flags.
+ * This is important for e.g. ARM_CP_SVE so that we still
+ * take the SVE trap if CPTR_EL3.EZ == 0.
+ */
+ r_const.type = (r->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
+ /*
+ * Usually, these registers become RES0, but there are a few
+ * special cases like VPIDR_EL2 which have a constant non-zero
+ * value with writes ignored.
+ */
+ if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
+ r_const.resetvalue = 0;
+ }
+ /*
+ * ARM_CP_CONST has precedence, so removing the callbacks and
+ * offsets are not strictly necessary, but it is potentially
+ * less confusing to debug later.
+ */
+ r_const.readfn = NULL;
+ r_const.writefn = NULL;
+ r_const.raw_readfn = NULL;
+ r_const.raw_writefn = NULL;
+ r_const.resetfn = NULL;
+ r_const.fieldoffset = 0;
+ r_const.bank_fieldoffsets[0] = 0;
+ r_const.bank_fieldoffsets[1] = 0;
+
+ r = &r_const;
+ }
+ }
+ } else {
+ CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
+ ? PL2_RW : PL1_RW);
+ if ((r->access & max_el) == 0) {
+ return;
+ }
+ }
+
for (int crm = crmmin; crm <= crmmax; crm++) {
for (int opc1 = opc1min; opc1 <= opc1max; opc1++) {
for (int opc2 = opc2min; opc2 <= opc2max; opc2++) {
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 26/44] target/arm: Add key parameter to add_cpreg_to_hashtable
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2025-09-26 14:08 ` [PULL 25/44] target/arm: Move cpreg elimination " Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 27/44] target/arm: Split out alloc_cpreg Peter Maydell
` (18 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Hoist the computation of key into the caller, where
state is a known constant.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMM: added comment about CRN key field increment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ade16138e75..8a8fa8c40e9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7369,26 +7369,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
CPState state, CPSecureState secstate,
int cp, int crm, int opc1, int opc2,
- const char *name)
+ const char *name, uint32_t key)
{
CPUARMState *env = &cpu->env;
- uint32_t key;
ARMCPRegInfo *r2;
- bool is64 = r->type & ARM_CP_64BIT;
bool ns = secstate & ARM_CP_SECSTATE_NS;
size_t name_len;
- switch (state) {
- case ARM_CP_STATE_AA32:
- key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
- break;
- case ARM_CP_STATE_AA64:
- key = ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2);
- break;
- default:
- g_assert_not_reached();
- }
-
/* Overriding of an existing definition must be explicitly requested. */
if (!(r->type & ARM_CP_OVERRIDE)) {
const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
@@ -7493,22 +7480,28 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r,
* (same for secure and non-secure world) or banked.
*/
char *name;
+ bool is64 = r->type & ARM_CP_64BIT;
+ uint32_t key = ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2);
assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */
switch (r->secure) {
- case ARM_CP_SECSTATE_S:
case ARM_CP_SECSTATE_NS:
+ key |= CP_REG_AA32_NS_MASK;
+ /* fall through */
+ case ARM_CP_SECSTATE_S:
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure,
- cp, crm, opc1, opc2, r->name);
+ cp, crm, opc1, opc2, r->name, key);
break;
case ARM_CP_SECSTATE_BOTH:
name = g_strdup_printf("%s_S", r->name);
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_S,
- cp, crm, opc1, opc2, name);
+ cp, crm, opc1, opc2, name, key);
g_free(name);
+
+ key |= CP_REG_AA32_NS_MASK;
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_NS,
- cp, crm, opc1, opc2, r->name);
+ cp, crm, opc1, opc2, r->name, key);
break;
default:
g_assert_not_reached();
@@ -7518,6 +7511,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r,
static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r,
int crm, int opc1, int opc2)
{
+ uint32_t key = ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2);
+
if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
cpu_isar_feature(aa64_xs, cpu)) {
/*
@@ -7532,18 +7527,23 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r,
*/
ARMCPRegInfo nxs_ri = *r;
g_autofree char *name = g_strdup_printf("%sNXS", r->name);
+ uint32_t nxs_key;
assert(nxs_ri.crn < 0xf);
nxs_ri.crn++;
+ /* Also increment the CRN field inside the key value */
+ nxs_key = key + (1 << CP_REG_ARM64_SYSREG_CRN_SHIFT);
if (nxs_ri.fgt) {
nxs_ri.fgt |= R_FGT_NXS_MASK;
}
+
add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64,
- ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, name);
+ ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2,
+ name, nxs_key);
}
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS,
- 0, crm, opc1, opc2, r->name);
+ 0, crm, opc1, opc2, r->name, key);
}
void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 27/44] target/arm: Split out alloc_cpreg
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2025-09-26 14:08 ` [PULL 26/44] target/arm: Add key parameter to add_cpreg_to_hashtable Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 28/44] target/arm: Hoist the allocation of ARMCPRegInfo Peter Maydell
` (17 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Include provision for a name suffix.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8a8fa8c40e9..e36598e273b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7362,6 +7362,28 @@ void register_cp_regs_for_features(ARMCPU *cpu)
#endif
}
+/*
+ * Copy a ARMCPRegInfo structure, allocating it along with the name
+ * and an optional suffix to the name.
+ */
+static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in,
+ const char *name, const char *suffix)
+{
+ size_t name_len = strlen(name);
+ size_t suff_len = suffix ? strlen(suffix) : 0;
+ ARMCPRegInfo *out = g_malloc(sizeof(*in) + name_len + suff_len + 1);
+ char *p = (char *)(out + 1);
+
+ *out = *in;
+ out->name = p;
+
+ memcpy(p, name, name_len + 1);
+ if (suffix) {
+ memcpy(p + name_len, suffix, suff_len + 1);
+ }
+ return out;
+}
+
/*
* Private utility function for define_one_arm_cp_reg():
* add a single reginfo struct to the hash table.
@@ -7374,7 +7396,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
CPUARMState *env = &cpu->env;
ARMCPRegInfo *r2;
bool ns = secstate & ARM_CP_SECSTATE_NS;
- size_t name_len;
/* Overriding of an existing definition must be explicitly requested. */
if (!(r->type & ARM_CP_OVERRIDE)) {
@@ -7384,11 +7405,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
}
}
- /* Combine cpreg and name into one allocation. */
- name_len = strlen(name) + 1;
- r2 = g_malloc(sizeof(*r2) + name_len);
- *r2 = *r;
- r2->name = memcpy(r2 + 1, name, name_len);
+ r2 = alloc_cpreg(r, name, NULL);
/*
* Update fields to match the instantiation, overwiting wildcards
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 28/44] target/arm: Hoist the allocation of ARMCPRegInfo
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2025-09-26 14:08 ` [PULL 27/44] target/arm: Split out alloc_cpreg Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 29/44] target/arm: Remove name argument to alloc_cpreg Peter Maydell
` (16 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Pass in a newly allocated structure, rather than having to
dance around allocation of the name and the structure.
Since we no longer have two copies of the structure handy
within add_cpreg_to_hashtable, delay the writeback of concrete
values over wildcards until we're done querying the wildcards.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 97 ++++++++++++++++++++++-----------------------
1 file changed, 48 insertions(+), 49 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e36598e273b..88b5ec1a5a2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7388,13 +7388,12 @@ static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in,
* Private utility function for define_one_arm_cp_reg():
* add a single reginfo struct to the hash table.
*/
-static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r,
CPState state, CPSecureState secstate,
int cp, int crm, int opc1, int opc2,
- const char *name, uint32_t key)
+ uint32_t key)
{
CPUARMState *env = &cpu->env;
- ARMCPRegInfo *r2;
bool ns = secstate & ARM_CP_SECSTATE_NS;
/* Overriding of an existing definition must be explicitly requested. */
@@ -7405,19 +7404,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
}
}
- r2 = alloc_cpreg(r, name, NULL);
-
- /*
- * Update fields to match the instantiation, overwiting wildcards
- * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
- */
- r2->cp = cp;
- r2->crm = crm;
- r2->opc1 = opc1;
- r2->opc2 = opc2;
- r2->state = state;
- r2->secure = secstate;
-
{
bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
@@ -7427,7 +7413,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
* Overwriting fieldoffset as the array is only used to define
* banked registers but later only fieldoffset is used.
*/
- r2->fieldoffset = r->bank_fieldoffsets[ns];
+ r->fieldoffset = r->bank_fieldoffsets[ns];
}
if (state == ARM_CP_STATE_AA32) {
if (isbanked) {
@@ -7444,19 +7430,19 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
*/
if ((r->state == ARM_CP_STATE_BOTH && ns) ||
(arm_feature(env, ARM_FEATURE_V8) && !ns)) {
- r2->type |= ARM_CP_ALIAS;
+ r->type |= ARM_CP_ALIAS;
}
} else if ((secstate != r->secure) && !ns) {
/*
* The register is not banked so we only want to allow
* migration of the non-secure instance.
*/
- r2->type |= ARM_CP_ALIAS;
+ r->type |= ARM_CP_ALIAS;
}
if (HOST_BIG_ENDIAN &&
- r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
- r2->fieldoffset += sizeof(uint32_t);
+ r->state == ARM_CP_STATE_BOTH && r->fieldoffset) {
+ r->fieldoffset += sizeof(uint32_t);
}
}
}
@@ -7468,35 +7454,46 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
* multiple times. Special registers (ie NOP/WFI) are
* never migratable and not even raw-accessible.
*/
- if (r2->type & ARM_CP_SPECIAL_MASK) {
- r2->type |= ARM_CP_NO_RAW;
+ if (r->type & ARM_CP_SPECIAL_MASK) {
+ r->type |= ARM_CP_NO_RAW;
}
if (((r->crm == CP_ANY) && crm != 0) ||
((r->opc1 == CP_ANY) && opc1 != 0) ||
((r->opc2 == CP_ANY) && opc2 != 0)) {
- r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
+ r->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
}
+ /*
+ * Update fields to match the instantiation, overwiting wildcards
+ * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
+ */
+ r->cp = cp;
+ r->crm = crm;
+ r->opc1 = opc1;
+ r->opc2 = opc2;
+ r->state = state;
+ r->secure = secstate;
+
/*
* Check that raw accesses are either forbidden or handled. Note that
* we can't assert this earlier because the setup of fieldoffset for
* banked registers has to be done first.
*/
- if (!(r2->type & ARM_CP_NO_RAW)) {
- assert(!raw_accessors_invalid(r2));
+ if (!(r->type & ARM_CP_NO_RAW)) {
+ assert(!raw_accessors_invalid(r));
}
- g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
+ g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r);
}
-static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r,
+static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r,
int cp, int crm, int opc1, int opc2)
{
/*
* Under AArch32 CP registers can be common
* (same for secure and non-secure world) or banked.
*/
- char *name;
+ ARMCPRegInfo *r_s;
bool is64 = r->type & ARM_CP_64BIT;
uint32_t key = ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2);
@@ -7508,24 +7505,23 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r,
/* fall through */
case ARM_CP_SECSTATE_S:
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure,
- cp, crm, opc1, opc2, r->name, key);
+ cp, crm, opc1, opc2, key);
break;
case ARM_CP_SECSTATE_BOTH:
- name = g_strdup_printf("%s_S", r->name);
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_S,
- cp, crm, opc1, opc2, name, key);
- g_free(name);
+ r_s = alloc_cpreg(r, r->name, "_S");
+ add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_S,
+ cp, crm, opc1, opc2, key);
key |= CP_REG_AA32_NS_MASK;
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_NS,
- cp, crm, opc1, opc2, r->name, key);
+ cp, crm, opc1, opc2, key);
break;
default:
g_assert_not_reached();
}
}
-static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r,
+static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r,
int crm, int opc1, int opc2)
{
uint32_t key = ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2);
@@ -7542,25 +7538,24 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r,
* and name that it is passed, so it's OK to use
* a local struct here.
*/
- ARMCPRegInfo nxs_ri = *r;
- g_autofree char *name = g_strdup_printf("%sNXS", r->name);
+ ARMCPRegInfo *nxs_ri = alloc_cpreg(r, r->name, "NXS");
uint32_t nxs_key;
- assert(nxs_ri.crn < 0xf);
- nxs_ri.crn++;
+ assert(nxs_ri->crn < 0xf);
+ nxs_ri->crn++;
/* Also increment the CRN field inside the key value */
nxs_key = key + (1 << CP_REG_ARM64_SYSREG_CRN_SHIFT);
- if (nxs_ri.fgt) {
- nxs_ri.fgt |= R_FGT_NXS_MASK;
+ if (nxs_ri->fgt) {
+ nxs_ri->fgt |= R_FGT_NXS_MASK;
}
- add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64,
+ add_cpreg_to_hashtable(cpu, nxs_ri, ARM_CP_STATE_AA64,
ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2,
- name, nxs_key);
+ nxs_key);
}
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS,
- 0, crm, opc1, opc2, r->name, key);
+ 0, crm, opc1, opc2, key);
}
void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
@@ -7767,16 +7762,20 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
for (int crm = crmmin; crm <= crmmax; crm++) {
for (int opc1 = opc1min; opc1 <= opc1max; opc1++) {
for (int opc2 = opc2min; opc2 <= opc2max; opc2++) {
+ ARMCPRegInfo *r2 = alloc_cpreg(r, r->name, NULL);
+ ARMCPRegInfo *r3;
+
switch (r->state) {
case ARM_CP_STATE_AA32:
- add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, opc2);
break;
case ARM_CP_STATE_AA64:
- add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2);
break;
case ARM_CP_STATE_BOTH:
- add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc2);
- add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2);
+ r3 = alloc_cpreg(r2, r2->name, NULL);
+ add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2);
break;
default:
g_assert_not_reached();
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 29/44] target/arm: Remove name argument to alloc_cpreg
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (27 preceding siblings ...)
2025-09-26 14:08 ` [PULL 28/44] target/arm: Hoist the allocation of ARMCPRegInfo Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 30/44] target/arm: Move alias setting for wildcards Peter Maydell
` (15 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
All callers now pass in->name, so take the value from there.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 88b5ec1a5a2..a199320f140 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7366,9 +7366,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
* Copy a ARMCPRegInfo structure, allocating it along with the name
* and an optional suffix to the name.
*/
-static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in,
- const char *name, const char *suffix)
+static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in, const char *suffix)
{
+ const char *name = in->name;
size_t name_len = strlen(name);
size_t suff_len = suffix ? strlen(suffix) : 0;
ARMCPRegInfo *out = g_malloc(sizeof(*in) + name_len + suff_len + 1);
@@ -7508,7 +7508,7 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r,
cp, crm, opc1, opc2, key);
break;
case ARM_CP_SECSTATE_BOTH:
- r_s = alloc_cpreg(r, r->name, "_S");
+ r_s = alloc_cpreg(r, "_S");
add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_S,
cp, crm, opc1, opc2, key);
@@ -7538,7 +7538,7 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r,
* and name that it is passed, so it's OK to use
* a local struct here.
*/
- ARMCPRegInfo *nxs_ri = alloc_cpreg(r, r->name, "NXS");
+ ARMCPRegInfo *nxs_ri = alloc_cpreg(r, "NXS");
uint32_t nxs_key;
assert(nxs_ri->crn < 0xf);
@@ -7762,7 +7762,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
for (int crm = crmmin; crm <= crmmax; crm++) {
for (int opc1 = opc1min; opc1 <= opc1max; opc1++) {
for (int opc2 = opc2min; opc2 <= opc2max; opc2++) {
- ARMCPRegInfo *r2 = alloc_cpreg(r, r->name, NULL);
+ ARMCPRegInfo *r2 = alloc_cpreg(r, NULL);
ARMCPRegInfo *r3;
switch (r->state) {
@@ -7773,7 +7773,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2);
break;
case ARM_CP_STATE_BOTH:
- r3 = alloc_cpreg(r2, r2->name, NULL);
+ r3 = alloc_cpreg(r2, NULL);
add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, opc2);
add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2);
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 30/44] target/arm: Move alias setting for wildcards
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (28 preceding siblings ...)
2025-09-26 14:08 ` [PULL 29/44] target/arm: Remove name argument to alloc_cpreg Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 31/44] target/arm: Move writeback of CP_ANY fields Peter Maydell
` (14 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Move this test from add_cpreg_to_hashtable to
define_one_arm_cp_reg_with_opaque, where we can also
simplify it based on the loop variables.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMM: adjusted placement of comma in a comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a199320f140..274b7b5808e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7448,20 +7448,12 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r,
}
/*
- * By convention, for wildcarded registers only the first
- * entry is used for migration; the others are marked as
- * ALIAS so we don't try to transfer the register
- * multiple times. Special registers (ie NOP/WFI) are
- * never migratable and not even raw-accessible.
+ * Special registers (ie NOP/WFI) are never migratable and
+ * are not even raw-accessible.
*/
if (r->type & ARM_CP_SPECIAL_MASK) {
r->type |= ARM_CP_NO_RAW;
}
- if (((r->crm == CP_ANY) && crm != 0) ||
- ((r->opc1 == CP_ANY) && opc1 != 0) ||
- ((r->opc2 == CP_ANY) && opc2 != 0)) {
- r->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
- }
/*
* Update fields to match the instantiation, overwiting wildcards
@@ -7765,6 +7757,16 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
ARMCPRegInfo *r2 = alloc_cpreg(r, NULL);
ARMCPRegInfo *r3;
+ /*
+ * By convention, for wildcarded registers only the first
+ * entry is used for migration; the others are marked as
+ * ALIAS so we don't try to transfer the register
+ * multiple times.
+ */
+ if (crm != crmmin || opc1 != opc1min || opc2 != opc2min) {
+ r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
+ }
+
switch (r->state) {
case ARM_CP_STATE_AA32:
add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, opc2);
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 31/44] target/arm: Move writeback of CP_ANY fields
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (29 preceding siblings ...)
2025-09-26 14:08 ` [PULL 30/44] target/arm: Move alias setting for wildcards Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 32/44] target/arm: Move endianness fixup for 32-bit registers Peter Maydell
` (13 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Move the writeback of cp, crm, opc1, opc2 to define_one_arm_cp_reg,
which means we don't have to pass all those parameters down
to subroutines.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 52 ++++++++++++++++++++++-----------------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 274b7b5808e..4063c8a0b6f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7390,7 +7390,6 @@ static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in, const char *suffix)
*/
static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r,
CPState state, CPSecureState secstate,
- int cp, int crm, int opc1, int opc2,
uint32_t key)
{
CPUARMState *env = &cpu->env;
@@ -7457,12 +7456,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r,
/*
* Update fields to match the instantiation, overwiting wildcards
- * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
+ * such as ARM_CP_STATE_BOTH or ARM_CP_SECSTATE_BOTH.
*/
- r->cp = cp;
- r->crm = crm;
- r->opc1 = opc1;
- r->opc2 = opc2;
r->state = state;
r->secure = secstate;
@@ -7478,8 +7473,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r,
g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r);
}
-static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r,
- int cp, int crm, int opc1, int opc2)
+static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r)
{
/*
* Under AArch32 CP registers can be common
@@ -7487,7 +7481,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r,
*/
ARMCPRegInfo *r_s;
bool is64 = r->type & ARM_CP_64BIT;
- uint32_t key = ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2);
+ uint32_t key = ENCODE_CP_REG(r->cp, is64, 0, r->crn,
+ r->crm, r->opc1, r->opc2);
assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */
@@ -7496,27 +7491,26 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r,
key |= CP_REG_AA32_NS_MASK;
/* fall through */
case ARM_CP_SECSTATE_S:
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure,
- cp, crm, opc1, opc2, key);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, key);
break;
case ARM_CP_SECSTATE_BOTH:
r_s = alloc_cpreg(r, "_S");
- add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_S,
- cp, crm, opc1, opc2, key);
+ add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32,
+ ARM_CP_SECSTATE_S, key);
key |= CP_REG_AA32_NS_MASK;
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_NS,
- cp, crm, opc1, opc2, key);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
+ ARM_CP_SECSTATE_NS, key);
break;
default:
g_assert_not_reached();
}
}
-static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r,
- int crm, int opc1, int opc2)
+static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r)
{
- uint32_t key = ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2);
+ uint32_t key = ENCODE_AA64_CP_REG(r->opc0, r->opc1,
+ r->crn, r->crm, r->opc2);
if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
cpu_isar_feature(aa64_xs, cpu)) {
@@ -7542,12 +7536,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r,
}
add_cpreg_to_hashtable(cpu, nxs_ri, ARM_CP_STATE_AA64,
- ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2,
- nxs_key);
+ ARM_CP_SECSTATE_NS, nxs_key);
}
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS,
- 0, crm, opc1, opc2, key);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64,
+ ARM_CP_SECSTATE_NS, key);
}
void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
@@ -7767,17 +7760,24 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
}
+ /* Overwrite CP_ANY with the instantiation. */
+ r2->crm = crm;
+ r2->opc1 = opc1;
+ r2->opc2 = opc2;
+
switch (r->state) {
case ARM_CP_STATE_AA32:
- add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa32(cpu, r2);
break;
case ARM_CP_STATE_AA64:
- add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa64(cpu, r2);
break;
case ARM_CP_STATE_BOTH:
r3 = alloc_cpreg(r2, NULL);
- add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, opc2);
- add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2);
+ r2->cp = cp;
+ add_cpreg_to_hashtable_aa32(cpu, r2);
+ r3->cp = 0;
+ add_cpreg_to_hashtable_aa64(cpu, r3);
break;
default:
g_assert_not_reached();
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 32/44] target/arm: Move endianness fixup for 32-bit registers
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (30 preceding siblings ...)
2025-09-26 14:08 ` [PULL 31/44] target/arm: Move writeback of CP_ANY fields Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 33/44] target/arm: Rename TBFLAG_A64_NV2_MEM_E20 with *_E2H Peter Maydell
` (12 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Move the test outside of the banked register block,
and repeat the AA32 test.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4063c8a0b6f..18066b0c5dc 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7438,14 +7438,21 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r,
*/
r->type |= ARM_CP_ALIAS;
}
-
- if (HOST_BIG_ENDIAN &&
- r->state == ARM_CP_STATE_BOTH && r->fieldoffset) {
- r->fieldoffset += sizeof(uint32_t);
- }
}
}
+ /*
+ * For 32-bit AArch32 regs shared with 64-bit AArch64 regs,
+ * adjust the field offset for endianness. This had to be
+ * delayed until banked registers were resolved.
+ */
+ if (HOST_BIG_ENDIAN &&
+ state == ARM_CP_STATE_AA32 &&
+ r->state == ARM_CP_STATE_BOTH &&
+ r->fieldoffset) {
+ r->fieldoffset += sizeof(uint32_t);
+ }
+
/*
* Special registers (ie NOP/WFI) are never migratable and
* are not even raw-accessible.
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 33/44] target/arm: Rename TBFLAG_A64_NV2_MEM_E20 with *_E2H
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (31 preceding siblings ...)
2025-09-26 14:08 ` [PULL 32/44] target/arm: Move endianness fixup for 32-bit registers Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 34/44] target/arm: Split out redirect_cpreg Peter Maydell
` (11 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Install e2h in tbflags and compute nv2_mem_e20 from
that in aarch64_tr_init_disas_context.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 3 +--
target/arm/tcg/translate.h | 2 ++
target/arm/tcg/hflags.c | 8 +++++---
target/arm/tcg/translate-a64.c | 3 ++-
4 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1c0deb723d7..d5534e35804 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3065,8 +3065,7 @@ FIELD(TBFLAG_A64, ATA0, 31, 1)
FIELD(TBFLAG_A64, NV, 32, 1)
FIELD(TBFLAG_A64, NV1, 33, 1)
FIELD(TBFLAG_A64, NV2, 34, 1)
-/* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */
-FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1)
+FIELD(TBFLAG_A64, E2H, 35, 1)
/* Set if FEAT_NV2 RAM accesses are big-endian */
FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index ec4755ae3fd..f1a6e5e2b61 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -150,6 +150,8 @@ typedef struct DisasContext {
bool trap_eret;
/* True if FEAT_LSE2 SCTLR_ELx.nAA is set */
bool naa;
+ /* True if HCR_EL2.E2H is set */
+ bool e2h;
/* True if FEAT_NV HCR_EL2.NV is enabled */
bool nv;
/* True if NV enabled and HCR_EL2.NV1 is set */
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
index 01894226cc9..17f83f13a40 100644
--- a/target/arm/tcg/hflags.c
+++ b/target/arm/tcg/hflags.c
@@ -258,6 +258,11 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
DP_TBFLAG_A64(flags, TBII, tbii);
DP_TBFLAG_A64(flags, TBID, tbid);
+ /* E2H is used by both VHE and NV2. */
+ if (hcr & HCR_E2H) {
+ DP_TBFLAG_A64(flags, E2H, 1);
+ }
+
if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
int sve_el = sve_exception_el(env, el);
@@ -390,9 +395,6 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
}
if (hcr & HCR_NV2) {
DP_TBFLAG_A64(flags, NV2, 1);
- if (hcr & HCR_E2H) {
- DP_TBFLAG_A64(flags, NV2_MEM_E20, 1);
- }
if (env->cp15.sctlr_el[2] & SCTLR_EE) {
DP_TBFLAG_A64(flags, NV2_MEM_BE, 1);
}
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 0ec309f1ea9..599e7a36ee3 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -10304,10 +10304,11 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);
dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING);
dc->naa = EX_TBFLAG_A64(tb_flags, NAA);
+ dc->e2h = EX_TBFLAG_A64(tb_flags, E2H);
dc->nv = EX_TBFLAG_A64(tb_flags, NV);
dc->nv1 = EX_TBFLAG_A64(tb_flags, NV1);
dc->nv2 = EX_TBFLAG_A64(tb_flags, NV2);
- dc->nv2_mem_e20 = EX_TBFLAG_A64(tb_flags, NV2_MEM_E20);
+ dc->nv2_mem_e20 = dc->nv2 && dc->e2h;
dc->nv2_mem_be = EX_TBFLAG_A64(tb_flags, NV2_MEM_BE);
dc->fpcr_ah = EX_TBFLAG_A64(tb_flags, AH);
dc->fpcr_nep = EX_TBFLAG_A64(tb_flags, NEP);
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 34/44] target/arm: Split out redirect_cpreg
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (32 preceding siblings ...)
2025-09-26 14:08 ` [PULL 33/44] target/arm: Rename TBFLAG_A64_NV2_MEM_E20 with *_E2H Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 35/44] target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation Peter Maydell
` (10 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-a64.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 599e7a36ee3..c0fa2137b63 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -2455,6 +2455,19 @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
}
+/*
+ * Look up @key, returning the cpreg, which must exist.
+ * Additionally, the new cpreg must also be accessible.
+ */
+static const ARMCPRegInfo *
+redirect_cpreg(DisasContext *s, uint32_t key, bool isread)
+{
+ const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
+ assert(ri);
+ assert(cp_access_ok(s->current_el, ri, isread));
+ return ri;
+}
+
/* MRS - move from system register
* MSR (register) - move to system register
* SYS
@@ -2603,9 +2616,7 @@ static void handle_sys(DisasContext *s, bool isread,
* fine-grained-traps on EL1 also do not apply here.
*/
key = ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2);
- ri = get_arm_cp_reginfo(s->cp_regs, key);
- assert(ri);
- assert(cp_access_ok(s->current_el, ri, isread));
+ ri = redirect_cpreg(s, key, isread);
/*
* We might not have done an update_pc earlier, so check we don't
* need it. We could support this in future if necessary.
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 35/44] target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (33 preceding siblings ...)
2025-09-26 14:08 ` [PULL 34/44] target/arm: Split out redirect_cpreg Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 36/44] target/arm: Redirect VHE FOO_EL12 to FOO_EL1 " Peter Maydell
` (9 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 6 ++++
target/arm/gdbstub.c | 5 ++++
target/arm/helper.c | 53 +---------------------------------
target/arm/tcg/translate-a64.c | 9 ++++++
4 files changed, 21 insertions(+), 52 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 08fc42ea571..eac0cb9ebf1 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -936,6 +936,12 @@ struct ARMCPRegInfo {
*/
uint32_t nv2_redirect_offset;
+ /*
+ * With VHE, with E2H, at EL2, access to this EL0/EL1 reg redirects
+ * to the EL2 reg with the specified key.
+ */
+ uint32_t vhe_redir_to_el2;
+
/* This is used only by VHE. */
void *opaque;
/*
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 4e2ac49b6a9..87d40d4366b 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -249,6 +249,11 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg)
if (ri) {
switch (cpreg_field_type(ri)) {
case MO_64:
+ if (ri->vhe_redir_to_el2 &&
+ (arm_hcr_el2_eff(env) & HCR_E2H) &&
+ arm_current_el(env) == 2) {
+ ri = get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_el2);
+ }
return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
case MO_32:
return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 18066b0c5dc..87a32e363e9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4417,47 +4417,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
return e2h_access(env, ri, isread);
}
-/* Test if system register redirection is to occur in the current state. */
-static bool redirect_for_e2h(CPUARMState *env)
-{
- return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H);
-}
-
-static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
- CPReadFn *readfn;
-
- if (redirect_for_e2h(env)) {
- /* Switch to the saved EL2 version of the register. */
- ri = ri->opaque;
- readfn = ri->readfn;
- } else {
- readfn = ri->orig_readfn;
- }
- if (readfn == NULL) {
- readfn = raw_read;
- }
- return readfn(env, ri);
-}
-
-static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
-{
- CPWriteFn *writefn;
-
- if (redirect_for_e2h(env)) {
- /* Switch to the saved EL2 version of the register. */
- ri = ri->opaque;
- writefn = ri->writefn;
- } else {
- writefn = ri->orig_writefn;
- }
- if (writefn == NULL) {
- writefn = raw_write;
- }
- writefn(env, ri, value);
-}
-
static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Pass the EL1 register accessor its ri, not the EL12 alias ri */
@@ -4632,17 +4591,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
(gpointer)(uintptr_t)a->new_key, new_reg);
g_assert(ok);
- src_reg->opaque = dst_reg;
- src_reg->orig_readfn = src_reg->readfn ?: raw_read;
- src_reg->orig_writefn = src_reg->writefn ?: raw_write;
- if (!src_reg->raw_readfn) {
- src_reg->raw_readfn = raw_read;
- }
- if (!src_reg->raw_writefn) {
- src_reg->raw_writefn = raw_write;
- }
- src_reg->readfn = el2_e2h_read;
- src_reg->writefn = el2_e2h_write;
+ src_reg->vhe_redir_to_el2 = a->dst_key;
}
}
#endif
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index c0fa2137b63..3ef24fb0c3d 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -2573,6 +2573,15 @@ static void handle_sys(DisasContext *s, bool isread,
}
}
+ if (ri->vhe_redir_to_el2 && s->current_el == 2 && s->e2h) {
+ /*
+ * This one of the FOO_EL1 registers which redirect to FOO_EL2
+ * from EL2 when HCR_EL2.E2H is set.
+ */
+ key = ri->vhe_redir_to_el2;
+ ri = redirect_cpreg(s, key, isread);
+ }
+
if (ri->accessfn || (ri->fgt && s->fgt_active)) {
/* Emit code to perform further access permissions checks at
* runtime; this may result in an exception.
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 36/44] target/arm: Redirect VHE FOO_EL12 to FOO_EL1 during translation
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (34 preceding siblings ...)
2025-09-26 14:08 ` [PULL 35/44] target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 37/44] target/arm: Rename some cpreg to their aarch64 names Peter Maydell
` (8 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMM: expanded a comment slightly]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 22 ++++---------
target/arm/gdbstub.c | 2 ++
target/arm/helper.c | 57 +++-------------------------------
target/arm/tcg/translate-a64.c | 12 +++++++
4 files changed, 25 insertions(+), 68 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index eac0cb9ebf1..8ab5892acce 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -942,8 +942,12 @@ struct ARMCPRegInfo {
*/
uint32_t vhe_redir_to_el2;
- /* This is used only by VHE. */
- void *opaque;
+ /*
+ * With VHE, with E2H, at EL2+, access to this EL02/EL12 reg
+ * redirects to the EL0/EL1 reg with the specified key.
+ */
+ uint32_t vhe_redir_to_el01;
+
/*
* Value of this register, if it is ARM_CP_CONST. Otherwise, if
* fieldoffset is non-zero, the reset value of the register.
@@ -1011,20 +1015,6 @@ struct ARMCPRegInfo {
* fieldoffset is 0 then no reset will be done.
*/
CPResetFn *resetfn;
-
- /*
- * "Original" readfn, writefn, accessfn.
- * For ARMv8.1-VHE register aliases, we overwrite the read/write
- * accessor functions of various EL1/EL0 to perform the runtime
- * check for which sysreg should actually be modified, and then
- * forwards the operation. Before overwriting the accessors,
- * the original function is copied here, so that accesses that
- * really do go to the EL1/EL0 version proceed normally.
- * (The corresponding EL2 register is linked via opaque.)
- */
- CPReadFn *orig_readfn;
- CPWriteFn *orig_writefn;
- CPAccessFn *orig_accessfn;
};
void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 87d40d4366b..8d2229f5192 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -253,6 +253,8 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg)
(arm_hcr_el2_eff(env) & HCR_E2H) &&
arm_current_el(env) == 2) {
ri = get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_el2);
+ } else if (ri->vhe_redir_to_el01) {
+ ri = get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_el01);
}
return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
case MO_32:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 87a32e363e9..3840ca62a69 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4417,42 +4417,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
return e2h_access(env, ri, isread);
}
-static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
- /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
- return ri->orig_readfn(env, ri->opaque);
-}
-
-static void el2_e2h_e12_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
-{
- /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
- return ri->orig_writefn(env, ri->opaque, value);
-}
-
-static CPAccessResult el2_e2h_e12_access(CPUARMState *env,
- const ARMCPRegInfo *ri,
- bool isread)
-{
- if (arm_current_el(env) == 1) {
- /*
- * This must be a FEAT_NV access (will either trap or redirect
- * to memory). None of the registers with _EL12 aliases want to
- * apply their trap controls for this kind of access, so don't
- * call the orig_accessfn or do the "UNDEF when E2H is 0" check.
- */
- return CP_ACCESS_OK;
- }
- /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */
- if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
- return CP_ACCESS_UNDEFINED;
- }
- if (ri->orig_accessfn) {
- return ri->orig_accessfn(env, ri->opaque, isread);
- }
- return CP_ACCESS_OK;
-}
-
static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
{
struct E2HAlias {
@@ -4541,9 +4505,6 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
g_assert(strcmp(src_reg->name, a->src_name) == 0);
g_assert(strcmp(dst_reg->name, a->dst_name) == 0);
- /* None of the core system registers use opaque; we will. */
- g_assert(src_reg->opaque == NULL);
-
/* Create alias before redirection so we dup the right data. */
new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
@@ -4562,19 +4523,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
>> CP_REG_ARM64_SYSREG_OP1_SHIFT;
new_reg->opc2 = (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK)
>> CP_REG_ARM64_SYSREG_OP2_SHIFT;
- new_reg->opaque = src_reg;
- new_reg->orig_readfn = src_reg->readfn ?: raw_read;
- new_reg->orig_writefn = src_reg->writefn ?: raw_write;
- new_reg->orig_accessfn = src_reg->accessfn;
- if (!new_reg->raw_readfn) {
- new_reg->raw_readfn = raw_read;
- }
- if (!new_reg->raw_writefn) {
- new_reg->raw_writefn = raw_write;
- }
- new_reg->readfn = el2_e2h_e12_read;
- new_reg->writefn = el2_e2h_e12_write;
- new_reg->accessfn = el2_e2h_e12_access;
+ new_reg->vhe_redir_to_el01 = a->src_key;
+ new_reg->readfn = NULL;
+ new_reg->writefn = NULL;
+ new_reg->accessfn = NULL;
+ new_reg->fieldoffset = 0;
/*
* If the _EL1 register is redirected to memory by FEAT_NV2,
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 3ef24fb0c3d..a0e3300231f 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -2580,6 +2580,18 @@ static void handle_sys(DisasContext *s, bool isread,
*/
key = ri->vhe_redir_to_el2;
ri = redirect_cpreg(s, key, isread);
+ } else if (ri->vhe_redir_to_el01 && s->current_el >= 2) {
+ /*
+ * This is one of the FOO_EL12 or FOO_EL02 registers.
+ * With !E2H, they all UNDEF.
+ * With E2H, from EL2 or EL3, they redirect to FOO_EL1/FOO_EL0.
+ */
+ if (!s->e2h) {
+ gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt);
+ return;
+ }
+ key = ri->vhe_redir_to_el01;
+ ri = redirect_cpreg(s, key, isread);
}
if (ri->accessfn || (ri->fgt && s->fgt_active)) {
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 37/44] target/arm: Rename some cpreg to their aarch64 names
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (35 preceding siblings ...)
2025-09-26 14:08 ` [PULL 36/44] target/arm: Redirect VHE FOO_EL12 to FOO_EL1 " Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 38/44] target/arm: Remove define_arm_vh_e2h_redirects_aliases Peter Maydell
` (7 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Rename those registers which will have FOO_EL12 aliases.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3840ca62a69..12835977bd8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -671,7 +671,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
*/
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
- { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
+ { .name = "CPACR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
.fgt = FGT_CPACR_EL1,
.nv2_redirect_offset = 0x100 | NV2_REDIR_NV1,
@@ -2018,7 +2018,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
.resetfn = arm_gt_cntfrq_reset,
},
/* overall control: mostly access permissions */
- { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
+ { .name = "CNTKCTL_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
.access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
@@ -3048,8 +3048,8 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
}
static const ARMCPRegInfo lpae_cp_reginfo[] = {
- /* NOP AMAIR0/1 */
- { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
+ /* AMAIR0 is mapped to AMAIR_EL1[31:0] */
+ { .name = "AMAIR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_AMAIR_EL1,
@@ -4430,11 +4430,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
static const struct E2HAlias aliases[] = {
{ K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
- "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
+ "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" },
{ K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3),
"SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sctlr2 },
{ K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
- "CPACR", "CPTR_EL2", "CPACR_EL12" },
+ "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" },
{ K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
"TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
{ K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
@@ -4458,13 +4458,13 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
{ K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
"MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
{ K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
- "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
+ "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" },
{ K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
- "VBAR", "VBAR_EL2", "VBAR_EL12" },
+ "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" },
{ K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
"CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
{ K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
- "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
+ "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" },
{ K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
"ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
@@ -7098,7 +7098,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_VBAR)) {
static const ARMCPRegInfo vbar_cp_reginfo[] = {
- { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
+ { .name = "VBAR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
.accessfn = access_nv1,
@@ -7114,7 +7114,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
- .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
+ .name = "SCTLR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_SCTLR_EL1,
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 38/44] target/arm: Remove define_arm_vh_e2h_redirects_aliases
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (36 preceding siblings ...)
2025-09-26 14:08 ` [PULL 37/44] target/arm: Rename some cpreg to their aarch64 names Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 39/44] target/arm: Replace magic GIC values by proper definitions Peter Maydell
` (6 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Populate vhe_redir_to_{el2,el01} on each ARMCPRegInfo.
Clear the fields within add_cpreg_to_hashtable_aa32.
Create the FOO_EL12 cpreg within add_cpreg_to_hashtable_aa64;
add ARM_CP_NO_RAW.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 6 +-
target/arm/helper.c | 243 +++++++++++++++++++-------------------------
2 files changed, 107 insertions(+), 142 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 8ab5892acce..57fde5f57ae 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -943,8 +943,10 @@ struct ARMCPRegInfo {
uint32_t vhe_redir_to_el2;
/*
- * With VHE, with E2H, at EL2+, access to this EL02/EL12 reg
- * redirects to the EL0/EL1 reg with the specified key.
+ * For VHE. Before registration, this field holds the key for an
+ * EL02/EL12 reg to be created to point back to this EL0/EL1 reg.
+ * After registration, this field is set only on the EL02/EL12 reg
+ * and points back to the EL02/EL12 reg for redirection with E2H.
*/
uint32_t vhe_redir_to_el01;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 12835977bd8..c5a8ef50493 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -454,6 +454,8 @@ static const ARMCPRegInfo cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_CONTEXTIDR_EL1,
.nv2_redirect_offset = 0x108 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 13, 0, 1),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 13, 0, 1),
.secure = ARM_CP_SECSTATE_NS,
.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
@@ -674,6 +676,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
{ .name = "CPACR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
.fgt = FGT_CPACR_EL1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 1, 1, 2),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 1, 0, 2),
.nv2_redirect_offset = 0x100 | NV2_REDIR_NV1,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
.resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
@@ -956,12 +960,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_AFSR0_EL1,
.nv2_redirect_offset = 0x128 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 5, 1, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 5, 1, 0),
.type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_AFSR1_EL1,
.nv2_redirect_offset = 0x130 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 5, 1, 1),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 5, 1, 1),
.type = ARM_CP_CONST, .resetvalue = 0 },
/*
* MAIR can just read-as-written because we don't implement caches
@@ -972,6 +980,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_MAIR_EL1,
.nv2_redirect_offset = 0x140 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 10, 2, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 10, 2, 0),
.fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
.resetvalue = 0 },
{ .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
@@ -2021,6 +2031,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = "CNTKCTL_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
.access = PL1_RW,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 14, 1, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 14, 1, 0),
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
.resetvalue = 0,
},
@@ -2811,6 +2823,8 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_FAR_EL1,
.nv2_redirect_offset = 0x220 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 6, 0, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 6, 0, 0),
.fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
.resetvalue = 0, },
};
@@ -2821,12 +2835,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_ESR_EL1,
.nv2_redirect_offset = 0x138 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 5, 2, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 5, 2, 0),
.fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_TTBR0_EL1,
.nv2_redirect_offset = 0x200 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 0, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 0, 0),
.writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
offsetof(CPUARMState, cp15.ttbr0_ns) } },
@@ -2835,6 +2853,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_TTBR1_EL1,
.nv2_redirect_offset = 0x210 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 0, 1),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 0, 1),
.writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
offsetof(CPUARMState, cp15.ttbr1_ns) } },
@@ -2843,6 +2863,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_TCR_EL1,
.nv2_redirect_offset = 0x120 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 0, 2),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 0, 2),
.writefn = vmsa_tcr_el12_write,
.raw_writefn = raw_write,
.resetvalue = 0,
@@ -3054,6 +3076,8 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_AMAIR_EL1,
.nv2_redirect_offset = 0x148 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 10, 3, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 10, 3, 0),
.type = ARM_CP_CONST, .resetvalue = 0 },
/* AMAIR1 is mapped to AMAIR_EL1[63:32] */
{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
@@ -3569,12 +3593,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
.access = PL1_RW, .accessfn = access_nv1,
.nv2_redirect_offset = 0x230 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 4, 0, 1),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 4, 0, 1),
.fieldoffset = offsetof(CPUARMState, elr_el[1]) },
{ .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_ALIAS,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
.access = PL1_RW, .accessfn = access_nv1,
.nv2_redirect_offset = 0x160 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 4, 0, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 4, 0, 0),
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
/*
* We rely on the access checks not allowing the guest to write to the
@@ -4417,136 +4445,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
return e2h_access(env, ri, isread);
}
-static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
-{
- struct E2HAlias {
- uint32_t src_key, dst_key, new_key;
- const char *src_name, *dst_name, *new_name;
- bool (*feature)(const ARMISARegisters *id);
- };
-
-#define K(op0, op1, crn, crm, op2) \
- ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2)
-
- static const struct E2HAlias aliases[] = {
- { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
- "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" },
- { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3),
- "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sctlr2 },
- { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
- "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" },
- { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
- "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
- { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
- "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
- { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
- "TCR_EL1", "TCR_EL2", "TCR_EL12" },
- { K(3, 0, 2, 0, 3), K(3, 4, 2, 0, 3), K(3, 5, 2, 0, 3),
- "TCR2_EL1", "TCR2_EL2", "TCR2_EL12", isar_feature_aa64_tcr2 },
- { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
- "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
- { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
- "ELR_EL1", "ELR_EL2", "ELR_EL12" },
- { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
- "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
- { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
- "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
- { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
- "ESR_EL1", "ESR_EL2", "ESR_EL12" },
- { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
- "FAR_EL1", "FAR_EL2", "FAR_EL12" },
- { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
- "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
- { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
- "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" },
- { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
- "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" },
- { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
- "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
- { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
- "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" },
-
- { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
- "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
- { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
- "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme },
-
- { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
- "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
-
- { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
- "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
- isar_feature_aa64_scxtnum },
-
- /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
- /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
- };
-#undef K
-
- size_t i;
-
- for (i = 0; i < ARRAY_SIZE(aliases); i++) {
- const struct E2HAlias *a = &aliases[i];
- ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
- bool ok;
-
- if (a->feature && !a->feature(&cpu->isar)) {
- continue;
- }
-
- src_reg = g_hash_table_lookup(cpu->cp_regs,
- (gpointer)(uintptr_t)a->src_key);
- dst_reg = g_hash_table_lookup(cpu->cp_regs,
- (gpointer)(uintptr_t)a->dst_key);
- g_assert(src_reg != NULL);
- g_assert(dst_reg != NULL);
-
- /* Cross-compare names to detect typos in the keys. */
- g_assert(strcmp(src_reg->name, a->src_name) == 0);
- g_assert(strcmp(dst_reg->name, a->dst_name) == 0);
-
- /* Create alias before redirection so we dup the right data. */
- new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-
- new_reg->name = a->new_name;
- new_reg->type |= ARM_CP_ALIAS;
- /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
- new_reg->access &= PL2_RW | PL3_RW;
- /* The new_reg op fields are as per new_key, not the target reg */
- new_reg->crn = (a->new_key & CP_REG_ARM64_SYSREG_CRN_MASK)
- >> CP_REG_ARM64_SYSREG_CRN_SHIFT;
- new_reg->crm = (a->new_key & CP_REG_ARM64_SYSREG_CRM_MASK)
- >> CP_REG_ARM64_SYSREG_CRM_SHIFT;
- new_reg->opc0 = (a->new_key & CP_REG_ARM64_SYSREG_OP0_MASK)
- >> CP_REG_ARM64_SYSREG_OP0_SHIFT;
- new_reg->opc1 = (a->new_key & CP_REG_ARM64_SYSREG_OP1_MASK)
- >> CP_REG_ARM64_SYSREG_OP1_SHIFT;
- new_reg->opc2 = (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK)
- >> CP_REG_ARM64_SYSREG_OP2_SHIFT;
- new_reg->vhe_redir_to_el01 = a->src_key;
- new_reg->readfn = NULL;
- new_reg->writefn = NULL;
- new_reg->accessfn = NULL;
- new_reg->fieldoffset = 0;
-
- /*
- * If the _EL1 register is redirected to memory by FEAT_NV2,
- * then it shares the offset with the _EL12 register,
- * and which one is redirected depends on HCR_EL2.NV1.
- */
- if (new_reg->nv2_redirect_offset) {
- assert(new_reg->nv2_redirect_offset & NV2_REDIR_NV1);
- new_reg->nv2_redirect_offset &= ~NV2_REDIR_NV1;
- new_reg->nv2_redirect_offset |= NV2_REDIR_NO_NV1;
- }
-
- ok = g_hash_table_insert(cpu->cp_regs,
- (gpointer)(uintptr_t)a->new_key, new_reg);
- g_assert(ok);
-
- src_reg->vhe_redir_to_el2 = a->dst_key;
- }
-}
#endif
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4839,6 +4737,8 @@ static const ARMCPRegInfo zcr_reginfo[] = {
{ .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
.nv2_redirect_offset = 0x1e0 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 1, 2, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 1, 2, 0),
.access = PL1_RW, .type = ARM_CP_SVE,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
.writefn = zcr_write, .raw_writefn = raw_write },
@@ -4984,6 +4884,8 @@ static const ARMCPRegInfo sme_reginfo[] = {
{ .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6,
.nv2_redirect_offset = 0x1f0 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 1, 2, 6),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 1, 2, 6),
.access = PL1_RW, .type = ARM_CP_SME,
.fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]),
.writefn = smcr_write, .raw_writefn = raw_write },
@@ -5429,6 +5331,8 @@ static const ARMCPRegInfo mte_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tfsr_el1,
.nv2_redirect_offset = 0x190 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 5, 6, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 5, 6, 0),
.fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) },
{ .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NV2_REDIRECT,
@@ -5604,6 +5508,8 @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
.access = PL1_RW, .accessfn = access_scxtnum_el1,
.fgt = FGT_SCXTNUM_EL1,
.nv2_redirect_offset = 0x188 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 13, 0, 7),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 13, 0, 7),
.fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
{ .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
@@ -5948,6 +5854,8 @@ static const ARMCPRegInfo sctlr2_reginfo[] = {
.opc0 = 3, .opc1 = 0, .opc2 = 3, .crn = 1, .crm = 0,
.access = PL1_RW, .accessfn = sctlr2_el1_access,
.writefn = sctlr2_el1_write, .fgt = FGT_SCTLR_EL1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 1, 0, 3),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 1, 0, 3),
.nv2_redirect_offset = 0x278 | NV2_REDIR_NV1,
.fieldoffset = offsetof(CPUARMState, cp15.sctlr2_el[1]) },
{ .name = "SCTLR2_EL2", .state = ARM_CP_STATE_AA64,
@@ -6008,6 +5916,8 @@ static const ARMCPRegInfo tcr2_reginfo[] = {
.opc0 = 3, .opc1 = 0, .opc2 = 3, .crn = 2, .crm = 0,
.access = PL1_RW, .accessfn = tcr2_el1_access,
.writefn = tcr2_el1_write, .fgt = FGT_TCR_EL1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 0, 3),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 0, 3),
.nv2_redirect_offset = 0x270 | NV2_REDIR_NV1,
.fieldoffset = offsetof(CPUARMState, cp15.tcr2_el[1]) },
{ .name = "TCR2_EL2", .state = ARM_CP_STATE_AA64,
@@ -7104,6 +7014,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = access_nv1,
.fgt = FGT_VBAR_EL1,
.nv2_redirect_offset = 0x250 | NV2_REDIR_NV1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 12, 0, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 12, 0, 0),
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
offsetof(CPUARMState, cp15.vbar_ns) },
.resetvalue = 0 },
@@ -7118,6 +7030,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fgt = FGT_SCTLR_EL1,
+ .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 1, 0, 0),
+ .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 1, 0, 0),
.nv2_redirect_offset = 0x110 | NV2_REDIR_NV1,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
offsetof(CPUARMState, cp15.sctlr_ns) },
@@ -7252,16 +7166,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
define_pm_cpregs(cpu);
-
-#ifndef CONFIG_USER_ONLY
- /*
- * Register redirections and aliases must be done last,
- * after the registers from the other extensions have been defined.
- */
- if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
- define_arm_vh_e2h_redirects_aliases(cpu);
- }
-#endif
}
/*
@@ -7394,6 +7298,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r)
r->crm, r->opc1, r->opc2);
assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */
+ r->vhe_redir_to_el2 = 0;
+ r->vhe_redir_to_el01 = 0;
switch (r->secure) {
case ARM_CP_SECSTATE_NS:
@@ -7448,6 +7354,63 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r)
ARM_CP_SECSTATE_NS, nxs_key);
}
+ if (!r->vhe_redir_to_el01) {
+ assert(!r->vhe_redir_to_el2);
+ } else if (!arm_feature(&cpu->env, ARM_FEATURE_EL2) ||
+ !cpu_isar_feature(aa64_vh, cpu)) {
+ r->vhe_redir_to_el2 = 0;
+ r->vhe_redir_to_el01 = 0;
+ } else {
+ /* Create the FOO_EL12 alias. */
+ ARMCPRegInfo *r2 = alloc_cpreg(r, "2");
+ uint32_t key2 = r->vhe_redir_to_el01;
+
+ /*
+ * Clear EL1 redirection on the FOO_EL1 reg;
+ * Clear EL2 redirection on the FOO_EL12 reg;
+ * Install redirection from FOO_EL12 back to FOO_EL1.
+ */
+ r->vhe_redir_to_el01 = 0;
+ r2->vhe_redir_to_el2 = 0;
+ r2->vhe_redir_to_el01 = key;
+
+ r2->type |= ARM_CP_ALIAS | ARM_CP_NO_RAW;
+ /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
+ r2->access &= PL2_RW | PL3_RW;
+ /* The new_reg op fields are as per new_key, not the target reg */
+ r2->crn = (key2 & CP_REG_ARM64_SYSREG_CRN_MASK)
+ >> CP_REG_ARM64_SYSREG_CRN_SHIFT;
+ r2->crm = (key2 & CP_REG_ARM64_SYSREG_CRM_MASK)
+ >> CP_REG_ARM64_SYSREG_CRM_SHIFT;
+ r2->opc0 = (key2 & CP_REG_ARM64_SYSREG_OP0_MASK)
+ >> CP_REG_ARM64_SYSREG_OP0_SHIFT;
+ r2->opc1 = (key2 & CP_REG_ARM64_SYSREG_OP1_MASK)
+ >> CP_REG_ARM64_SYSREG_OP1_SHIFT;
+ r2->opc2 = (key2 & CP_REG_ARM64_SYSREG_OP2_MASK)
+ >> CP_REG_ARM64_SYSREG_OP2_SHIFT;
+
+ /* Non-redirected access to this register will abort. */
+ r2->readfn = NULL;
+ r2->writefn = NULL;
+ r2->raw_readfn = NULL;
+ r2->raw_writefn = NULL;
+ r2->accessfn = NULL;
+ r2->fieldoffset = 0;
+
+ /*
+ * If the _EL1 register is redirected to memory by FEAT_NV2,
+ * then it shares the offset with the _EL12 register,
+ * and which one is redirected depends on HCR_EL2.NV1.
+ */
+ if (r2->nv2_redirect_offset) {
+ assert(r2->nv2_redirect_offset & NV2_REDIR_NV1);
+ r2->nv2_redirect_offset &= ~NV2_REDIR_NV1;
+ r2->nv2_redirect_offset |= NV2_REDIR_NO_NV1;
+ }
+ add_cpreg_to_hashtable(cpu, r2, ARM_CP_STATE_AA64,
+ ARM_CP_SECSTATE_NS, key2);
+ }
+
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64,
ARM_CP_SECSTATE_NS, key);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 39/44] target/arm: Replace magic GIC values by proper definitions
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (37 preceding siblings ...)
2025-09-26 14:08 ` [PULL 38/44] target/arm: Remove define_arm_vh_e2h_redirects_aliases Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 40/44] target/arm: Convert power control DPRINTF() uses to trace events Peter Maydell
` (5 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Prefer the FIELD_DP64() macro and self-describing GIC
definitions over magic values.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c5a8ef50493..a18d920ac18 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5007,7 +5007,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
uint64_t pfr1 = GET_IDREG(&cpu->isar, ID_PFR1);
if (env->gicv3state) {
- pfr1 |= 1 << 28;
+ pfr1 = FIELD_DP64(pfr1, ID_PFR1, GIC, 1);
}
return pfr1;
}
@@ -5018,7 +5018,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
uint64_t pfr0 = GET_IDREG(&cpu->isar, ID_AA64PFR0);
if (env->gicv3state) {
- pfr0 |= 1 << 24;
+ pfr0 = FIELD_DP64(pfr0, ID_AA64PFR0, GIC, 1);
}
return pfr0;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 40/44] target/arm: Convert power control DPRINTF() uses to trace events
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (38 preceding siblings ...)
2025-09-26 14:08 ` [PULL 39/44] target/arm: Replace magic GIC values by proper definitions Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 41/44] target/arm: Trace emulated firmware reset call Peter Maydell
` (4 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/arm-powerctl.c | 26 ++++++++------------------
target/arm/trace-events | 6 ++++++
2 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index 20c70c7d6bb..a788376d1d3 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -17,24 +17,12 @@
#include "qemu/main-loop.h"
#include "system/tcg.h"
#include "target/arm/multiprocessing.h"
-
-#ifndef DEBUG_ARM_POWERCTL
-#define DEBUG_ARM_POWERCTL 0
-#endif
-
-#define DPRINTF(fmt, args...) \
- do { \
- if (DEBUG_ARM_POWERCTL) { \
- fprintf(stderr, "[ARM]%s: " fmt , __func__, ##args); \
- } \
- } while (0)
+#include "trace.h"
CPUState *arm_get_cpu_by_id(uint64_t id)
{
CPUState *cpu;
- DPRINTF("cpu %" PRId64 "\n", id);
-
CPU_FOREACH(cpu) {
ARMCPU *armcpu = ARM_CPU(cpu);
@@ -102,9 +90,9 @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
assert(bql_locked());
- DPRINTF("cpu %" PRId64 " (EL %d, %s) @ 0x%" PRIx64 " with R0 = 0x%" PRIx64
- "\n", cpuid, target_el, target_aa64 ? "aarch64" : "aarch32", entry,
- context_id);
+ trace_arm_powerctl_set_cpu_on(cpuid, target_el,
+ target_aa64 ? "aarch64" : "aarch32",
+ entry, context_id);
/* requested EL level need to be in the 1 to 3 range */
assert((target_el > 0) && (target_el < 4));
@@ -208,6 +196,8 @@ int arm_set_cpu_on_and_reset(uint64_t cpuid)
assert(bql_locked());
+ trace_arm_powerctl_set_cpu_on_and_reset(cpuid);
+
/* Retrieve the cpu we are powering up */
target_cpu_state = arm_get_cpu_by_id(cpuid);
if (!target_cpu_state) {
@@ -261,7 +251,7 @@ int arm_set_cpu_off(uint64_t cpuid)
assert(bql_locked());
- DPRINTF("cpu %" PRId64 "\n", cpuid);
+ trace_arm_powerctl_set_cpu_off(cpuid);
/* change to the cpu we are powering up */
target_cpu_state = arm_get_cpu_by_id(cpuid);
@@ -297,7 +287,7 @@ int arm_reset_cpu(uint64_t cpuid)
assert(bql_locked());
- DPRINTF("cpu %" PRId64 "\n", cpuid);
+ trace_arm_powerctl_set_cpu_off(cpuid);
/* change to the cpu we are resetting */
target_cpu_state = arm_get_cpu_by_id(cpuid);
diff --git a/target/arm/trace-events b/target/arm/trace-events
index 4438dce7bec..252c05a9ebe 100644
--- a/target/arm/trace-events
+++ b/target/arm/trace-events
@@ -13,3 +13,9 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
# kvm.c
kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64
+
+# arm-powerctl.c
+arm_powerctl_set_cpu_on(uint64_t mp_aff, unsigned target_el, const char *mode, uint64_t entry, uint64_t context_id) "cpu %" PRIu64 " (EL %u, %s) @ 0x%" PRIx64 " with R0 = 0x%" PRIx64
+arm_powerctl_set_cpu_on_and_reset(uint64_t mp_aff) "cpu %" PRIu64
+arm_powerctl_set_cpu_off(uint64_t mp_aff) "cpu %" PRIu64
+arm_powerctl_reset_cpu(uint64_t mp_aff) "cpu %" PRIu64
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 41/44] target/arm: Trace emulated firmware reset call
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (39 preceding siblings ...)
2025-09-26 14:08 ` [PULL 40/44] target/arm: Convert power control DPRINTF() uses to trace events Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 42/44] target/arm: Trace vCPU " Peter Maydell
` (3 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 4 ++++
target/arm/trace-events | 3 +++
2 files changed, 7 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 91ae56dddb2..f8e6749ff99 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -52,6 +52,8 @@
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
+#include "trace.h"
+
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -574,6 +576,8 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
+ trace_arm_emulate_firmware_reset(arm_cpu_mp_affinity(cpu), target_el);
+
/*
* Check we have the EL we're aiming for. If that is the
* highest implemented EL, then cpu_reset has already done
diff --git a/target/arm/trace-events b/target/arm/trace-events
index 252c05a9ebe..badff2b2e46 100644
--- a/target/arm/trace-events
+++ b/target/arm/trace-events
@@ -14,6 +14,9 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
# kvm.c
kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64
+# cpu.c
+arm_emulate_firmware_reset(uint64_t mp_aff, unsigned target_el) "cpu %" PRIu64 " @EL%u"
+
# arm-powerctl.c
arm_powerctl_set_cpu_on(uint64_t mp_aff, unsigned target_el, const char *mode, uint64_t entry, uint64_t context_id) "cpu %" PRIu64 " (EL %u, %s) @ 0x%" PRIx64 " with R0 = 0x%" PRIx64
arm_powerctl_set_cpu_on_and_reset(uint64_t mp_aff) "cpu %" PRIu64
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 42/44] target/arm: Trace vCPU reset call
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (40 preceding siblings ...)
2025-09-26 14:08 ` [PULL 41/44] target/arm: Trace emulated firmware reset call Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 43/44] target/arm: Move ID register field defs to cpu-features.h Peter Maydell
` (2 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 2 ++
target/arm/trace-events | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f8e6749ff99..30e29fd3153 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -227,6 +227,8 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
CPUARMState *env = &cpu->env;
+ trace_arm_cpu_reset(arm_cpu_mp_affinity(cpu));
+
if (acc->parent_phases.hold) {
acc->parent_phases.hold(obj, type);
}
diff --git a/target/arm/trace-events b/target/arm/trace-events
index badff2b2e46..72a2c7d0969 100644
--- a/target/arm/trace-events
+++ b/target/arm/trace-events
@@ -15,6 +15,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64
# cpu.c
+arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64
arm_emulate_firmware_reset(uint64_t mp_aff, unsigned target_el) "cpu %" PRIu64 " @EL%u"
# arm-powerctl.c
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 43/44] target/arm: Move ID register field defs to cpu-features.h
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (41 preceding siblings ...)
2025-09-26 14:08 ` [PULL 42/44] target/arm: Trace vCPU " Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-26 14:08 ` [PULL 44/44] target/arm: Implement ID_AA64PFR2_EL1 Peter Maydell
2025-09-27 15:42 ` [PULL 00/44] target-arm queue Richard Henderson
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
Currently we define constants for the ID register fields in cpu.h.
This means they're defined for a lot more code in QEMU than actually
needs them. Move them to cpu-features.h, which is where we define
the feature functions that test fields in these registers.
There's only one place where we need to use some of these macro
definitions that we weren't already including cpu-features.h:
linux-user/arm/target_proc.h. Otherwise this patch is a pure
movement of code from one file to the other.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/arm/target_proc.h | 2 +
target/arm/cpu-features.h | 410 +++++++++++++++++++++++++++++++++++
target/arm/cpu.h | 410 -----------------------------------
3 files changed, 412 insertions(+), 410 deletions(-)
diff --git a/linux-user/arm/target_proc.h b/linux-user/arm/target_proc.h
index a4cd6948c60..a28d7231cdc 100644
--- a/linux-user/arm/target_proc.h
+++ b/linux-user/arm/target_proc.h
@@ -6,6 +6,8 @@
#ifndef ARM_TARGET_PROC_H
#define ARM_TARGET_PROC_H
+#include "target/arm/cpu-features.h" /* for MIDR_EL1 field definitions */
+
static int open_cpuinfo(CPUArchState *cpu_env, int fd)
{
ARMCPU *cpu = env_archcpu(cpu_env);
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 512eeaf551e..ad571e2ffee 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -25,6 +25,416 @@
#include "cpu.h"
#include "cpu-sysregs.h"
+/*
+ * System register ID fields.
+ */
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
+FIELD(CLIDR_EL1, LOC, 24, 3)
+FIELD(CLIDR_EL1, LOUU, 27, 3)
+FIELD(CLIDR_EL1, ICB, 30, 3)
+
+/* When FEAT_CCIDX is implemented */
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
+
+/* When FEAT_CCIDX is not implemented */
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
+
+FIELD(CTR_EL0, IMINLINE, 0, 4)
+FIELD(CTR_EL0, L1IP, 14, 2)
+FIELD(CTR_EL0, DMINLINE, 16, 4)
+FIELD(CTR_EL0, ERG, 20, 4)
+FIELD(CTR_EL0, CWG, 24, 4)
+FIELD(CTR_EL0, IDC, 28, 1)
+FIELD(CTR_EL0, DIC, 29, 1)
+FIELD(CTR_EL0, TMINLINE, 32, 6)
+
+FIELD(MIDR_EL1, REVISION, 0, 4)
+FIELD(MIDR_EL1, PARTNUM, 4, 12)
+FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
+FIELD(MIDR_EL1, VARIANT, 20, 4)
+FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
+
+FIELD(ID_ISAR0, SWAP, 0, 4)
+FIELD(ID_ISAR0, BITCOUNT, 4, 4)
+FIELD(ID_ISAR0, BITFIELD, 8, 4)
+FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
+FIELD(ID_ISAR0, COPROC, 16, 4)
+FIELD(ID_ISAR0, DEBUG, 20, 4)
+FIELD(ID_ISAR0, DIVIDE, 24, 4)
+
+FIELD(ID_ISAR1, ENDIAN, 0, 4)
+FIELD(ID_ISAR1, EXCEPT, 4, 4)
+FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
+FIELD(ID_ISAR1, EXTEND, 12, 4)
+FIELD(ID_ISAR1, IFTHEN, 16, 4)
+FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
+FIELD(ID_ISAR1, INTERWORK, 24, 4)
+FIELD(ID_ISAR1, JAZELLE, 28, 4)
+
+FIELD(ID_ISAR2, LOADSTORE, 0, 4)
+FIELD(ID_ISAR2, MEMHINT, 4, 4)
+FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
+FIELD(ID_ISAR2, MULT, 12, 4)
+FIELD(ID_ISAR2, MULTS, 16, 4)
+FIELD(ID_ISAR2, MULTU, 20, 4)
+FIELD(ID_ISAR2, PSR_AR, 24, 4)
+FIELD(ID_ISAR2, REVERSAL, 28, 4)
+
+FIELD(ID_ISAR3, SATURATE, 0, 4)
+FIELD(ID_ISAR3, SIMD, 4, 4)
+FIELD(ID_ISAR3, SVC, 8, 4)
+FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
+FIELD(ID_ISAR3, TABBRANCH, 16, 4)
+FIELD(ID_ISAR3, T32COPY, 20, 4)
+FIELD(ID_ISAR3, TRUENOP, 24, 4)
+FIELD(ID_ISAR3, T32EE, 28, 4)
+
+FIELD(ID_ISAR4, UNPRIV, 0, 4)
+FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
+FIELD(ID_ISAR4, WRITEBACK, 8, 4)
+FIELD(ID_ISAR4, SMC, 12, 4)
+FIELD(ID_ISAR4, BARRIER, 16, 4)
+FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
+FIELD(ID_ISAR4, PSR_M, 24, 4)
+FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
+
+FIELD(ID_ISAR5, SEVL, 0, 4)
+FIELD(ID_ISAR5, AES, 4, 4)
+FIELD(ID_ISAR5, SHA1, 8, 4)
+FIELD(ID_ISAR5, SHA2, 12, 4)
+FIELD(ID_ISAR5, CRC32, 16, 4)
+FIELD(ID_ISAR5, RDM, 24, 4)
+FIELD(ID_ISAR5, VCMA, 28, 4)
+
+FIELD(ID_ISAR6, JSCVT, 0, 4)
+FIELD(ID_ISAR6, DP, 4, 4)
+FIELD(ID_ISAR6, FHM, 8, 4)
+FIELD(ID_ISAR6, SB, 12, 4)
+FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_ISAR6, BF16, 20, 4)
+FIELD(ID_ISAR6, I8MM, 24, 4)
+
+FIELD(ID_MMFR0, VMSA, 0, 4)
+FIELD(ID_MMFR0, PMSA, 4, 4)
+FIELD(ID_MMFR0, OUTERSHR, 8, 4)
+FIELD(ID_MMFR0, SHARELVL, 12, 4)
+FIELD(ID_MMFR0, TCM, 16, 4)
+FIELD(ID_MMFR0, AUXREG, 20, 4)
+FIELD(ID_MMFR0, FCSE, 24, 4)
+FIELD(ID_MMFR0, INNERSHR, 28, 4)
+
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
+FIELD(ID_MMFR1, L1HVD, 16, 4)
+FIELD(ID_MMFR1, L1UNI, 20, 4)
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
+FIELD(ID_MMFR1, BPRED, 28, 4)
+
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
+FIELD(ID_MMFR2, UNITLB, 16, 4)
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
+
+FIELD(ID_MMFR3, CMAINTVA, 0, 4)
+FIELD(ID_MMFR3, CMAINTSW, 4, 4)
+FIELD(ID_MMFR3, BPMAINT, 8, 4)
+FIELD(ID_MMFR3, MAINTBCST, 12, 4)
+FIELD(ID_MMFR3, PAN, 16, 4)
+FIELD(ID_MMFR3, COHWALK, 20, 4)
+FIELD(ID_MMFR3, CMEMSZ, 24, 4)
+FIELD(ID_MMFR3, SUPERSEC, 28, 4)
+
+FIELD(ID_MMFR4, SPECSEI, 0, 4)
+FIELD(ID_MMFR4, AC2, 4, 4)
+FIELD(ID_MMFR4, XNX, 8, 4)
+FIELD(ID_MMFR4, CNP, 12, 4)
+FIELD(ID_MMFR4, HPDS, 16, 4)
+FIELD(ID_MMFR4, LSM, 20, 4)
+FIELD(ID_MMFR4, CCIDX, 24, 4)
+FIELD(ID_MMFR4, EVT, 28, 4)
+
+FIELD(ID_MMFR5, ETS, 0, 4)
+FIELD(ID_MMFR5, NTLBPA, 4, 4)
+
+FIELD(ID_PFR0, STATE0, 0, 4)
+FIELD(ID_PFR0, STATE1, 4, 4)
+FIELD(ID_PFR0, STATE2, 8, 4)
+FIELD(ID_PFR0, STATE3, 12, 4)
+FIELD(ID_PFR0, CSV2, 16, 4)
+FIELD(ID_PFR0, AMU, 20, 4)
+FIELD(ID_PFR0, DIT, 24, 4)
+FIELD(ID_PFR0, RAS, 28, 4)
+
+FIELD(ID_PFR1, PROGMOD, 0, 4)
+FIELD(ID_PFR1, SECURITY, 4, 4)
+FIELD(ID_PFR1, MPROGMOD, 8, 4)
+FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
+FIELD(ID_PFR1, GENTIMER, 16, 4)
+FIELD(ID_PFR1, SEC_FRAC, 20, 4)
+FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
+FIELD(ID_PFR1, GIC, 28, 4)
+
+FIELD(ID_PFR2, CSV3, 0, 4)
+FIELD(ID_PFR2, SSBS, 4, 4)
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
+
+FIELD(ID_AA64ISAR0, AES, 4, 4)
+FIELD(ID_AA64ISAR0, SHA1, 8, 4)
+FIELD(ID_AA64ISAR0, SHA2, 12, 4)
+FIELD(ID_AA64ISAR0, CRC32, 16, 4)
+FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
+FIELD(ID_AA64ISAR0, TME, 24, 4)
+FIELD(ID_AA64ISAR0, RDM, 28, 4)
+FIELD(ID_AA64ISAR0, SHA3, 32, 4)
+FIELD(ID_AA64ISAR0, SM3, 36, 4)
+FIELD(ID_AA64ISAR0, SM4, 40, 4)
+FIELD(ID_AA64ISAR0, DP, 44, 4)
+FIELD(ID_AA64ISAR0, FHM, 48, 4)
+FIELD(ID_AA64ISAR0, TS, 52, 4)
+FIELD(ID_AA64ISAR0, TLB, 56, 4)
+FIELD(ID_AA64ISAR0, RNDR, 60, 4)
+
+FIELD(ID_AA64ISAR1, DPB, 0, 4)
+FIELD(ID_AA64ISAR1, APA, 4, 4)
+FIELD(ID_AA64ISAR1, API, 8, 4)
+FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
+FIELD(ID_AA64ISAR1, FCMA, 16, 4)
+FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
+FIELD(ID_AA64ISAR1, GPA, 24, 4)
+FIELD(ID_AA64ISAR1, GPI, 28, 4)
+FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
+FIELD(ID_AA64ISAR1, SB, 36, 4)
+FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
+FIELD(ID_AA64ISAR1, XS, 56, 4)
+FIELD(ID_AA64ISAR1, LS64, 60, 4)
+
+FIELD(ID_AA64ISAR2, WFXT, 0, 4)
+FIELD(ID_AA64ISAR2, RPRES, 4, 4)
+FIELD(ID_AA64ISAR2, GPA3, 8, 4)
+FIELD(ID_AA64ISAR2, APA3, 12, 4)
+FIELD(ID_AA64ISAR2, MOPS, 16, 4)
+FIELD(ID_AA64ISAR2, BC, 20, 4)
+FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
+FIELD(ID_AA64ISAR2, CLRBHB, 28, 4)
+FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4)
+FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)
+FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)
+FIELD(ID_AA64ISAR2, RPRFM, 48, 4)
+FIELD(ID_AA64ISAR2, CSSC, 52, 4)
+FIELD(ID_AA64ISAR2, LUT, 56, 4)
+FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
+
+FIELD(ID_AA64PFR0, EL0, 0, 4)
+FIELD(ID_AA64PFR0, EL1, 4, 4)
+FIELD(ID_AA64PFR0, EL2, 8, 4)
+FIELD(ID_AA64PFR0, EL3, 12, 4)
+FIELD(ID_AA64PFR0, FP, 16, 4)
+FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
+FIELD(ID_AA64PFR0, GIC, 24, 4)
+FIELD(ID_AA64PFR0, RAS, 28, 4)
+FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, RME, 52, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
+
+FIELD(ID_AA64PFR1, BT, 0, 4)
+FIELD(ID_AA64PFR1, SSBS, 4, 4)
+FIELD(ID_AA64PFR1, MTE, 8, 4)
+FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
+FIELD(ID_AA64PFR1, SME, 24, 4)
+FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
+FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
+FIELD(ID_AA64PFR1, NMI, 36, 4)
+FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4)
+FIELD(ID_AA64PFR1, GCS, 44, 4)
+FIELD(ID_AA64PFR1, THE, 48, 4)
+FIELD(ID_AA64PFR1, MTEX, 52, 4)
+FIELD(ID_AA64PFR1, DF2, 56, 4)
+FIELD(ID_AA64PFR1, PFAR, 60, 4)
+
+FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
+FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
+FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
+FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
+FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
+FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
+FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
+FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
+FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
+FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
+FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
+FIELD(ID_AA64MMFR0, EXS, 44, 4)
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
+
+FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
+FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
+FIELD(ID_AA64MMFR1, VH, 8, 4)
+FIELD(ID_AA64MMFR1, HPDS, 12, 4)
+FIELD(ID_AA64MMFR1, LO, 16, 4)
+FIELD(ID_AA64MMFR1, PAN, 20, 4)
+FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
+FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
+FIELD(ID_AA64MMFR1, HCX, 40, 4)
+FIELD(ID_AA64MMFR1, AFP, 44, 4)
+FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
+FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
+FIELD(ID_AA64MMFR1, CMOW, 56, 4)
+FIELD(ID_AA64MMFR1, ECBHB, 60, 4)
+
+FIELD(ID_AA64MMFR2, CNP, 0, 4)
+FIELD(ID_AA64MMFR2, UAO, 4, 4)
+FIELD(ID_AA64MMFR2, LSM, 8, 4)
+FIELD(ID_AA64MMFR2, IESB, 12, 4)
+FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
+FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
+FIELD(ID_AA64MMFR2, NV, 24, 4)
+FIELD(ID_AA64MMFR2, ST, 28, 4)
+FIELD(ID_AA64MMFR2, AT, 32, 4)
+FIELD(ID_AA64MMFR2, IDS, 36, 4)
+FIELD(ID_AA64MMFR2, FWB, 40, 4)
+FIELD(ID_AA64MMFR2, TTL, 48, 4)
+FIELD(ID_AA64MMFR2, BBM, 52, 4)
+FIELD(ID_AA64MMFR2, EVT, 56, 4)
+FIELD(ID_AA64MMFR2, E0PD, 60, 4)
+
+FIELD(ID_AA64MMFR3, TCRX, 0, 4)
+FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
+FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
+FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
+FIELD(ID_AA64MMFR3, S1POE, 16, 4)
+FIELD(ID_AA64MMFR3, S2POE, 20, 4)
+FIELD(ID_AA64MMFR3, AIE, 24, 4)
+FIELD(ID_AA64MMFR3, MEC, 28, 4)
+FIELD(ID_AA64MMFR3, D128, 32, 4)
+FIELD(ID_AA64MMFR3, D128_2, 36, 4)
+FIELD(ID_AA64MMFR3, SNERR, 40, 4)
+FIELD(ID_AA64MMFR3, ANERR, 44, 4)
+FIELD(ID_AA64MMFR3, SDERR, 52, 4)
+FIELD(ID_AA64MMFR3, ADERR, 56, 4)
+FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
+
+FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
+FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
+FIELD(ID_AA64DFR0, PMUVER, 8, 4)
+FIELD(ID_AA64DFR0, BRPS, 12, 4)
+FIELD(ID_AA64DFR0, PMSS, 16, 4)
+FIELD(ID_AA64DFR0, WRPS, 20, 4)
+FIELD(ID_AA64DFR0, SEBEP, 24, 4)
+FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
+FIELD(ID_AA64DFR0, PMSVER, 32, 4)
+FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
+FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
+FIELD(ID_AA64DFR0, BRBE, 52, 4)
+FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4)
+FIELD(ID_AA64DFR0, HPMN0, 60, 4)
+
+FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
+FIELD(ID_AA64ZFR0, AES, 4, 4)
+FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
+FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
+FIELD(ID_AA64ZFR0, B16B16, 24, 4)
+FIELD(ID_AA64ZFR0, SHA3, 32, 4)
+FIELD(ID_AA64ZFR0, SM4, 40, 4)
+FIELD(ID_AA64ZFR0, I8MM, 44, 4)
+FIELD(ID_AA64ZFR0, F32MM, 52, 4)
+FIELD(ID_AA64ZFR0, F64MM, 56, 4)
+
+FIELD(ID_AA64SMFR0, F32F32, 32, 1)
+FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
+FIELD(ID_AA64SMFR0, B16F32, 34, 1)
+FIELD(ID_AA64SMFR0, F16F32, 35, 1)
+FIELD(ID_AA64SMFR0, I8I32, 36, 4)
+FIELD(ID_AA64SMFR0, F16F16, 42, 1)
+FIELD(ID_AA64SMFR0, B16B16, 43, 1)
+FIELD(ID_AA64SMFR0, I16I32, 44, 4)
+FIELD(ID_AA64SMFR0, F64F64, 48, 1)
+FIELD(ID_AA64SMFR0, I16I64, 52, 4)
+FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
+FIELD(ID_AA64SMFR0, FA64, 63, 1)
+
+FIELD(ID_DFR0, COPDBG, 0, 4)
+FIELD(ID_DFR0, COPSDBG, 4, 4)
+FIELD(ID_DFR0, MMAPDBG, 8, 4)
+FIELD(ID_DFR0, COPTRC, 12, 4)
+FIELD(ID_DFR0, MMAPTRC, 16, 4)
+FIELD(ID_DFR0, MPROFDBG, 20, 4)
+FIELD(ID_DFR0, PERFMON, 24, 4)
+FIELD(ID_DFR0, TRACEFILT, 28, 4)
+
+FIELD(ID_DFR1, MTPMU, 0, 4)
+FIELD(ID_DFR1, HPMN0, 4, 4)
+
+FIELD(DBGDIDR, SE_IMP, 12, 1)
+FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
+FIELD(DBGDIDR, VERSION, 16, 4)
+FIELD(DBGDIDR, CTX_CMPS, 20, 4)
+FIELD(DBGDIDR, BRPS, 24, 4)
+FIELD(DBGDIDR, WRPS, 28, 4)
+
+FIELD(DBGDEVID, PCSAMPLE, 0, 4)
+FIELD(DBGDEVID, WPADDRMASK, 4, 4)
+FIELD(DBGDEVID, BPADDRMASK, 8, 4)
+FIELD(DBGDEVID, VECTORCATCH, 12, 4)
+FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
+FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
+FIELD(DBGDEVID, AUXREGS, 24, 4)
+FIELD(DBGDEVID, CIDMASK, 28, 4)
+
+FIELD(DBGDEVID1, PCSROFFSET, 0, 4)
+
+FIELD(MVFR0, SIMDREG, 0, 4)
+FIELD(MVFR0, FPSP, 4, 4)
+FIELD(MVFR0, FPDP, 8, 4)
+FIELD(MVFR0, FPTRAP, 12, 4)
+FIELD(MVFR0, FPDIVIDE, 16, 4)
+FIELD(MVFR0, FPSQRT, 20, 4)
+FIELD(MVFR0, FPSHVEC, 24, 4)
+FIELD(MVFR0, FPROUND, 28, 4)
+
+FIELD(MVFR1, FPFTZ, 0, 4)
+FIELD(MVFR1, FPDNAN, 4, 4)
+FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
+FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
+FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
+FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
+FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
+FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
+FIELD(MVFR1, FPHP, 24, 4)
+FIELD(MVFR1, SIMDFMAC, 28, 4)
+
+FIELD(MVFR2, SIMDMISC, 0, 4)
+FIELD(MVFR2, FPMISC, 4, 4)
+
/*
* Naming convention for isar_feature functions:
* Functions which test 32-bit ID registers should have _aa32_ in
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d5534e35804..2b9585dc80a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1994,416 +1994,6 @@ FIELD(V7M_VPR, P0, 0, 16)
FIELD(V7M_VPR, MASK01, 16, 4)
FIELD(V7M_VPR, MASK23, 20, 4)
-/*
- * System register ID fields.
- */
-FIELD(CLIDR_EL1, CTYPE1, 0, 3)
-FIELD(CLIDR_EL1, CTYPE2, 3, 3)
-FIELD(CLIDR_EL1, CTYPE3, 6, 3)
-FIELD(CLIDR_EL1, CTYPE4, 9, 3)
-FIELD(CLIDR_EL1, CTYPE5, 12, 3)
-FIELD(CLIDR_EL1, CTYPE6, 15, 3)
-FIELD(CLIDR_EL1, CTYPE7, 18, 3)
-FIELD(CLIDR_EL1, LOUIS, 21, 3)
-FIELD(CLIDR_EL1, LOC, 24, 3)
-FIELD(CLIDR_EL1, LOUU, 27, 3)
-FIELD(CLIDR_EL1, ICB, 30, 3)
-
-/* When FEAT_CCIDX is implemented */
-FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
-FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
-FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
-
-/* When FEAT_CCIDX is not implemented */
-FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
-FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
-FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
-
-FIELD(CTR_EL0, IMINLINE, 0, 4)
-FIELD(CTR_EL0, L1IP, 14, 2)
-FIELD(CTR_EL0, DMINLINE, 16, 4)
-FIELD(CTR_EL0, ERG, 20, 4)
-FIELD(CTR_EL0, CWG, 24, 4)
-FIELD(CTR_EL0, IDC, 28, 1)
-FIELD(CTR_EL0, DIC, 29, 1)
-FIELD(CTR_EL0, TMINLINE, 32, 6)
-
-FIELD(MIDR_EL1, REVISION, 0, 4)
-FIELD(MIDR_EL1, PARTNUM, 4, 12)
-FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
-FIELD(MIDR_EL1, VARIANT, 20, 4)
-FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
-
-FIELD(ID_ISAR0, SWAP, 0, 4)
-FIELD(ID_ISAR0, BITCOUNT, 4, 4)
-FIELD(ID_ISAR0, BITFIELD, 8, 4)
-FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
-FIELD(ID_ISAR0, COPROC, 16, 4)
-FIELD(ID_ISAR0, DEBUG, 20, 4)
-FIELD(ID_ISAR0, DIVIDE, 24, 4)
-
-FIELD(ID_ISAR1, ENDIAN, 0, 4)
-FIELD(ID_ISAR1, EXCEPT, 4, 4)
-FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
-FIELD(ID_ISAR1, EXTEND, 12, 4)
-FIELD(ID_ISAR1, IFTHEN, 16, 4)
-FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
-FIELD(ID_ISAR1, INTERWORK, 24, 4)
-FIELD(ID_ISAR1, JAZELLE, 28, 4)
-
-FIELD(ID_ISAR2, LOADSTORE, 0, 4)
-FIELD(ID_ISAR2, MEMHINT, 4, 4)
-FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
-FIELD(ID_ISAR2, MULT, 12, 4)
-FIELD(ID_ISAR2, MULTS, 16, 4)
-FIELD(ID_ISAR2, MULTU, 20, 4)
-FIELD(ID_ISAR2, PSR_AR, 24, 4)
-FIELD(ID_ISAR2, REVERSAL, 28, 4)
-
-FIELD(ID_ISAR3, SATURATE, 0, 4)
-FIELD(ID_ISAR3, SIMD, 4, 4)
-FIELD(ID_ISAR3, SVC, 8, 4)
-FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
-FIELD(ID_ISAR3, TABBRANCH, 16, 4)
-FIELD(ID_ISAR3, T32COPY, 20, 4)
-FIELD(ID_ISAR3, TRUENOP, 24, 4)
-FIELD(ID_ISAR3, T32EE, 28, 4)
-
-FIELD(ID_ISAR4, UNPRIV, 0, 4)
-FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
-FIELD(ID_ISAR4, WRITEBACK, 8, 4)
-FIELD(ID_ISAR4, SMC, 12, 4)
-FIELD(ID_ISAR4, BARRIER, 16, 4)
-FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
-FIELD(ID_ISAR4, PSR_M, 24, 4)
-FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
-
-FIELD(ID_ISAR5, SEVL, 0, 4)
-FIELD(ID_ISAR5, AES, 4, 4)
-FIELD(ID_ISAR5, SHA1, 8, 4)
-FIELD(ID_ISAR5, SHA2, 12, 4)
-FIELD(ID_ISAR5, CRC32, 16, 4)
-FIELD(ID_ISAR5, RDM, 24, 4)
-FIELD(ID_ISAR5, VCMA, 28, 4)
-
-FIELD(ID_ISAR6, JSCVT, 0, 4)
-FIELD(ID_ISAR6, DP, 4, 4)
-FIELD(ID_ISAR6, FHM, 8, 4)
-FIELD(ID_ISAR6, SB, 12, 4)
-FIELD(ID_ISAR6, SPECRES, 16, 4)
-FIELD(ID_ISAR6, BF16, 20, 4)
-FIELD(ID_ISAR6, I8MM, 24, 4)
-
-FIELD(ID_MMFR0, VMSA, 0, 4)
-FIELD(ID_MMFR0, PMSA, 4, 4)
-FIELD(ID_MMFR0, OUTERSHR, 8, 4)
-FIELD(ID_MMFR0, SHARELVL, 12, 4)
-FIELD(ID_MMFR0, TCM, 16, 4)
-FIELD(ID_MMFR0, AUXREG, 20, 4)
-FIELD(ID_MMFR0, FCSE, 24, 4)
-FIELD(ID_MMFR0, INNERSHR, 28, 4)
-
-FIELD(ID_MMFR1, L1HVDVA, 0, 4)
-FIELD(ID_MMFR1, L1UNIVA, 4, 4)
-FIELD(ID_MMFR1, L1HVDSW, 8, 4)
-FIELD(ID_MMFR1, L1UNISW, 12, 4)
-FIELD(ID_MMFR1, L1HVD, 16, 4)
-FIELD(ID_MMFR1, L1UNI, 20, 4)
-FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
-FIELD(ID_MMFR1, BPRED, 28, 4)
-
-FIELD(ID_MMFR2, L1HVDFG, 0, 4)
-FIELD(ID_MMFR2, L1HVDBG, 4, 4)
-FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
-FIELD(ID_MMFR2, HVDTLB, 12, 4)
-FIELD(ID_MMFR2, UNITLB, 16, 4)
-FIELD(ID_MMFR2, MEMBARR, 20, 4)
-FIELD(ID_MMFR2, WFISTALL, 24, 4)
-FIELD(ID_MMFR2, HWACCFLG, 28, 4)
-
-FIELD(ID_MMFR3, CMAINTVA, 0, 4)
-FIELD(ID_MMFR3, CMAINTSW, 4, 4)
-FIELD(ID_MMFR3, BPMAINT, 8, 4)
-FIELD(ID_MMFR3, MAINTBCST, 12, 4)
-FIELD(ID_MMFR3, PAN, 16, 4)
-FIELD(ID_MMFR3, COHWALK, 20, 4)
-FIELD(ID_MMFR3, CMEMSZ, 24, 4)
-FIELD(ID_MMFR3, SUPERSEC, 28, 4)
-
-FIELD(ID_MMFR4, SPECSEI, 0, 4)
-FIELD(ID_MMFR4, AC2, 4, 4)
-FIELD(ID_MMFR4, XNX, 8, 4)
-FIELD(ID_MMFR4, CNP, 12, 4)
-FIELD(ID_MMFR4, HPDS, 16, 4)
-FIELD(ID_MMFR4, LSM, 20, 4)
-FIELD(ID_MMFR4, CCIDX, 24, 4)
-FIELD(ID_MMFR4, EVT, 28, 4)
-
-FIELD(ID_MMFR5, ETS, 0, 4)
-FIELD(ID_MMFR5, NTLBPA, 4, 4)
-
-FIELD(ID_PFR0, STATE0, 0, 4)
-FIELD(ID_PFR0, STATE1, 4, 4)
-FIELD(ID_PFR0, STATE2, 8, 4)
-FIELD(ID_PFR0, STATE3, 12, 4)
-FIELD(ID_PFR0, CSV2, 16, 4)
-FIELD(ID_PFR0, AMU, 20, 4)
-FIELD(ID_PFR0, DIT, 24, 4)
-FIELD(ID_PFR0, RAS, 28, 4)
-
-FIELD(ID_PFR1, PROGMOD, 0, 4)
-FIELD(ID_PFR1, SECURITY, 4, 4)
-FIELD(ID_PFR1, MPROGMOD, 8, 4)
-FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
-FIELD(ID_PFR1, GENTIMER, 16, 4)
-FIELD(ID_PFR1, SEC_FRAC, 20, 4)
-FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
-FIELD(ID_PFR1, GIC, 28, 4)
-
-FIELD(ID_PFR2, CSV3, 0, 4)
-FIELD(ID_PFR2, SSBS, 4, 4)
-FIELD(ID_PFR2, RAS_FRAC, 8, 4)
-
-FIELD(ID_AA64ISAR0, AES, 4, 4)
-FIELD(ID_AA64ISAR0, SHA1, 8, 4)
-FIELD(ID_AA64ISAR0, SHA2, 12, 4)
-FIELD(ID_AA64ISAR0, CRC32, 16, 4)
-FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
-FIELD(ID_AA64ISAR0, TME, 24, 4)
-FIELD(ID_AA64ISAR0, RDM, 28, 4)
-FIELD(ID_AA64ISAR0, SHA3, 32, 4)
-FIELD(ID_AA64ISAR0, SM3, 36, 4)
-FIELD(ID_AA64ISAR0, SM4, 40, 4)
-FIELD(ID_AA64ISAR0, DP, 44, 4)
-FIELD(ID_AA64ISAR0, FHM, 48, 4)
-FIELD(ID_AA64ISAR0, TS, 52, 4)
-FIELD(ID_AA64ISAR0, TLB, 56, 4)
-FIELD(ID_AA64ISAR0, RNDR, 60, 4)
-
-FIELD(ID_AA64ISAR1, DPB, 0, 4)
-FIELD(ID_AA64ISAR1, APA, 4, 4)
-FIELD(ID_AA64ISAR1, API, 8, 4)
-FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
-FIELD(ID_AA64ISAR1, FCMA, 16, 4)
-FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
-FIELD(ID_AA64ISAR1, GPA, 24, 4)
-FIELD(ID_AA64ISAR1, GPI, 28, 4)
-FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
-FIELD(ID_AA64ISAR1, SB, 36, 4)
-FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
-FIELD(ID_AA64ISAR1, BF16, 44, 4)
-FIELD(ID_AA64ISAR1, DGH, 48, 4)
-FIELD(ID_AA64ISAR1, I8MM, 52, 4)
-FIELD(ID_AA64ISAR1, XS, 56, 4)
-FIELD(ID_AA64ISAR1, LS64, 60, 4)
-
-FIELD(ID_AA64ISAR2, WFXT, 0, 4)
-FIELD(ID_AA64ISAR2, RPRES, 4, 4)
-FIELD(ID_AA64ISAR2, GPA3, 8, 4)
-FIELD(ID_AA64ISAR2, APA3, 12, 4)
-FIELD(ID_AA64ISAR2, MOPS, 16, 4)
-FIELD(ID_AA64ISAR2, BC, 20, 4)
-FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
-FIELD(ID_AA64ISAR2, CLRBHB, 28, 4)
-FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4)
-FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)
-FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)
-FIELD(ID_AA64ISAR2, RPRFM, 48, 4)
-FIELD(ID_AA64ISAR2, CSSC, 52, 4)
-FIELD(ID_AA64ISAR2, LUT, 56, 4)
-FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
-
-FIELD(ID_AA64PFR0, EL0, 0, 4)
-FIELD(ID_AA64PFR0, EL1, 4, 4)
-FIELD(ID_AA64PFR0, EL2, 8, 4)
-FIELD(ID_AA64PFR0, EL3, 12, 4)
-FIELD(ID_AA64PFR0, FP, 16, 4)
-FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
-FIELD(ID_AA64PFR0, GIC, 24, 4)
-FIELD(ID_AA64PFR0, RAS, 28, 4)
-FIELD(ID_AA64PFR0, SVE, 32, 4)
-FIELD(ID_AA64PFR0, SEL2, 36, 4)
-FIELD(ID_AA64PFR0, MPAM, 40, 4)
-FIELD(ID_AA64PFR0, AMU, 44, 4)
-FIELD(ID_AA64PFR0, DIT, 48, 4)
-FIELD(ID_AA64PFR0, RME, 52, 4)
-FIELD(ID_AA64PFR0, CSV2, 56, 4)
-FIELD(ID_AA64PFR0, CSV3, 60, 4)
-
-FIELD(ID_AA64PFR1, BT, 0, 4)
-FIELD(ID_AA64PFR1, SSBS, 4, 4)
-FIELD(ID_AA64PFR1, MTE, 8, 4)
-FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
-FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
-FIELD(ID_AA64PFR1, SME, 24, 4)
-FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
-FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
-FIELD(ID_AA64PFR1, NMI, 36, 4)
-FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4)
-FIELD(ID_AA64PFR1, GCS, 44, 4)
-FIELD(ID_AA64PFR1, THE, 48, 4)
-FIELD(ID_AA64PFR1, MTEX, 52, 4)
-FIELD(ID_AA64PFR1, DF2, 56, 4)
-FIELD(ID_AA64PFR1, PFAR, 60, 4)
-
-FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
-FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
-FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
-FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
-FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
-FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
-FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
-FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
-FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
-FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
-FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
-FIELD(ID_AA64MMFR0, EXS, 44, 4)
-FIELD(ID_AA64MMFR0, FGT, 56, 4)
-FIELD(ID_AA64MMFR0, ECV, 60, 4)
-
-FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
-FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
-FIELD(ID_AA64MMFR1, VH, 8, 4)
-FIELD(ID_AA64MMFR1, HPDS, 12, 4)
-FIELD(ID_AA64MMFR1, LO, 16, 4)
-FIELD(ID_AA64MMFR1, PAN, 20, 4)
-FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
-FIELD(ID_AA64MMFR1, XNX, 28, 4)
-FIELD(ID_AA64MMFR1, TWED, 32, 4)
-FIELD(ID_AA64MMFR1, ETS, 36, 4)
-FIELD(ID_AA64MMFR1, HCX, 40, 4)
-FIELD(ID_AA64MMFR1, AFP, 44, 4)
-FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
-FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
-FIELD(ID_AA64MMFR1, CMOW, 56, 4)
-FIELD(ID_AA64MMFR1, ECBHB, 60, 4)
-
-FIELD(ID_AA64MMFR2, CNP, 0, 4)
-FIELD(ID_AA64MMFR2, UAO, 4, 4)
-FIELD(ID_AA64MMFR2, LSM, 8, 4)
-FIELD(ID_AA64MMFR2, IESB, 12, 4)
-FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
-FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
-FIELD(ID_AA64MMFR2, NV, 24, 4)
-FIELD(ID_AA64MMFR2, ST, 28, 4)
-FIELD(ID_AA64MMFR2, AT, 32, 4)
-FIELD(ID_AA64MMFR2, IDS, 36, 4)
-FIELD(ID_AA64MMFR2, FWB, 40, 4)
-FIELD(ID_AA64MMFR2, TTL, 48, 4)
-FIELD(ID_AA64MMFR2, BBM, 52, 4)
-FIELD(ID_AA64MMFR2, EVT, 56, 4)
-FIELD(ID_AA64MMFR2, E0PD, 60, 4)
-
-FIELD(ID_AA64MMFR3, TCRX, 0, 4)
-FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
-FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
-FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
-FIELD(ID_AA64MMFR3, S1POE, 16, 4)
-FIELD(ID_AA64MMFR3, S2POE, 20, 4)
-FIELD(ID_AA64MMFR3, AIE, 24, 4)
-FIELD(ID_AA64MMFR3, MEC, 28, 4)
-FIELD(ID_AA64MMFR3, D128, 32, 4)
-FIELD(ID_AA64MMFR3, D128_2, 36, 4)
-FIELD(ID_AA64MMFR3, SNERR, 40, 4)
-FIELD(ID_AA64MMFR3, ANERR, 44, 4)
-FIELD(ID_AA64MMFR3, SDERR, 52, 4)
-FIELD(ID_AA64MMFR3, ADERR, 56, 4)
-FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
-
-FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
-FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
-FIELD(ID_AA64DFR0, PMUVER, 8, 4)
-FIELD(ID_AA64DFR0, BRPS, 12, 4)
-FIELD(ID_AA64DFR0, PMSS, 16, 4)
-FIELD(ID_AA64DFR0, WRPS, 20, 4)
-FIELD(ID_AA64DFR0, SEBEP, 24, 4)
-FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
-FIELD(ID_AA64DFR0, PMSVER, 32, 4)
-FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
-FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
-FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
-FIELD(ID_AA64DFR0, MTPMU, 48, 4)
-FIELD(ID_AA64DFR0, BRBE, 52, 4)
-FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4)
-FIELD(ID_AA64DFR0, HPMN0, 60, 4)
-
-FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
-FIELD(ID_AA64ZFR0, AES, 4, 4)
-FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
-FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
-FIELD(ID_AA64ZFR0, B16B16, 24, 4)
-FIELD(ID_AA64ZFR0, SHA3, 32, 4)
-FIELD(ID_AA64ZFR0, SM4, 40, 4)
-FIELD(ID_AA64ZFR0, I8MM, 44, 4)
-FIELD(ID_AA64ZFR0, F32MM, 52, 4)
-FIELD(ID_AA64ZFR0, F64MM, 56, 4)
-
-FIELD(ID_AA64SMFR0, F32F32, 32, 1)
-FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
-FIELD(ID_AA64SMFR0, B16F32, 34, 1)
-FIELD(ID_AA64SMFR0, F16F32, 35, 1)
-FIELD(ID_AA64SMFR0, I8I32, 36, 4)
-FIELD(ID_AA64SMFR0, F16F16, 42, 1)
-FIELD(ID_AA64SMFR0, B16B16, 43, 1)
-FIELD(ID_AA64SMFR0, I16I32, 44, 4)
-FIELD(ID_AA64SMFR0, F64F64, 48, 1)
-FIELD(ID_AA64SMFR0, I16I64, 52, 4)
-FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
-FIELD(ID_AA64SMFR0, FA64, 63, 1)
-
-FIELD(ID_DFR0, COPDBG, 0, 4)
-FIELD(ID_DFR0, COPSDBG, 4, 4)
-FIELD(ID_DFR0, MMAPDBG, 8, 4)
-FIELD(ID_DFR0, COPTRC, 12, 4)
-FIELD(ID_DFR0, MMAPTRC, 16, 4)
-FIELD(ID_DFR0, MPROFDBG, 20, 4)
-FIELD(ID_DFR0, PERFMON, 24, 4)
-FIELD(ID_DFR0, TRACEFILT, 28, 4)
-
-FIELD(ID_DFR1, MTPMU, 0, 4)
-FIELD(ID_DFR1, HPMN0, 4, 4)
-
-FIELD(DBGDIDR, SE_IMP, 12, 1)
-FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
-FIELD(DBGDIDR, VERSION, 16, 4)
-FIELD(DBGDIDR, CTX_CMPS, 20, 4)
-FIELD(DBGDIDR, BRPS, 24, 4)
-FIELD(DBGDIDR, WRPS, 28, 4)
-
-FIELD(DBGDEVID, PCSAMPLE, 0, 4)
-FIELD(DBGDEVID, WPADDRMASK, 4, 4)
-FIELD(DBGDEVID, BPADDRMASK, 8, 4)
-FIELD(DBGDEVID, VECTORCATCH, 12, 4)
-FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
-FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
-FIELD(DBGDEVID, AUXREGS, 24, 4)
-FIELD(DBGDEVID, CIDMASK, 28, 4)
-
-FIELD(DBGDEVID1, PCSROFFSET, 0, 4)
-
-FIELD(MVFR0, SIMDREG, 0, 4)
-FIELD(MVFR0, FPSP, 4, 4)
-FIELD(MVFR0, FPDP, 8, 4)
-FIELD(MVFR0, FPTRAP, 12, 4)
-FIELD(MVFR0, FPDIVIDE, 16, 4)
-FIELD(MVFR0, FPSQRT, 20, 4)
-FIELD(MVFR0, FPSHVEC, 24, 4)
-FIELD(MVFR0, FPROUND, 28, 4)
-
-FIELD(MVFR1, FPFTZ, 0, 4)
-FIELD(MVFR1, FPDNAN, 4, 4)
-FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
-FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
-FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
-FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
-FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
-FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
-FIELD(MVFR1, FPHP, 24, 4)
-FIELD(MVFR1, SIMDFMAC, 28, 4)
-
-FIELD(MVFR2, SIMDMISC, 0, 4)
-FIELD(MVFR2, FPMISC, 4, 4)
-
FIELD(GPCCR, PPS, 0, 3)
FIELD(GPCCR, IRGN, 8, 2)
FIELD(GPCCR, ORGN, 10, 2)
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PULL 44/44] target/arm: Implement ID_AA64PFR2_EL1
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (42 preceding siblings ...)
2025-09-26 14:08 ` [PULL 43/44] target/arm: Move ID register field defs to cpu-features.h Peter Maydell
@ 2025-09-26 14:08 ` Peter Maydell
2025-09-27 15:42 ` [PULL 00/44] target-arm queue Richard Henderson
44 siblings, 0 replies; 48+ messages in thread
From: Peter Maydell @ 2025-09-26 14:08 UTC (permalink / raw)
To: qemu-devel
Currently we define the ID_AA64PFR2_EL1 encoding as reserved (with
the required RAZ behaviour for unassigned system registers in the ID
register encoding space). Newer architecture versions start to
define fields in this ID register, so define the appropriate
constants and implement it as an ID register backed by a field in
cpu->isar. Since none of our CPUs set that isar field to non-zero,
there is no behavioural change here (other than the name exposed to
the user via the gdbstub), but this paves the way for implementing
the new features that use fields in this register.
The fields here are the ones documented in rev L.b of the Arm ARM.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-features.h | 5 +++++
target/arm/cpu-sysregs.h.inc | 1 +
target/arm/helper.c | 6 ++++--
target/arm/hvf/hvf.c | 1 +
target/arm/kvm.c | 1 +
target/arm/hvf/sysreg.c.inc | 1 +
6 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index ad571e2ffee..602f6a88e53 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -277,6 +277,11 @@ FIELD(ID_AA64PFR1, MTEX, 52, 4)
FIELD(ID_AA64PFR1, DF2, 56, 4)
FIELD(ID_AA64PFR1, PFAR, 60, 4)
+FIELD(ID_AA64PFR2, MTEPERM, 0, 4)
+FIELD(ID_AA64PFR2, MTESTOREONLY, 4, 4)
+FIELD(ID_AA64PFR2, MTEFAR, 8, 4)
+FIELD(ID_AA64PFR2, FPMR, 32, 4)
+
FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index f48a9daa7c1..2bb2861c623 100644
--- a/target/arm/cpu-sysregs.h.inc
+++ b/target/arm/cpu-sysregs.h.inc
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
+DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)
DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a18d920ac18..aa730addf2f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6109,11 +6109,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
.resetvalue = GET_IDREG(isar, ID_AA64PFR1)},
- { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+ { .name = "ID_AA64PFR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = 0 },
+ .resetvalue = GET_IDREG(isar, ID_AA64PFR2)},
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -6341,6 +6341,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
R_ID_AA64PFR1_SSBS_MASK |
R_ID_AA64PFR1_MTE_MASK |
R_ID_AA64PFR1_SME_MASK },
+ { .name = "ID_AA64PFR2_EL1",
+ .exported_bits = 0 },
{ .name = "ID_AA64PFR*_EL1_RESERVED",
.is_glob = true },
{ .name = "ID_AA64ZFR0_EL1",
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 8b467b36638..0658a99a2d1 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -744,6 +744,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
} regs[] = {
{ HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] },
{ HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] },
+ /* Add ID_AA64PFR2_EL1 here when HVF supports it */
{ HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] },
{ HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] },
{ HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 5a75ff59271..b8a1c071f57 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -324,6 +324,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err = 0;
} else {
err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR2_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX);
diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc
index f2276d534e6..067a8603fa7 100644
--- a/target/arm/hvf/sysreg.c.inc
+++ b/target/arm/hvf/sysreg.c.inc
@@ -92,6 +92,7 @@ DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
#endif
DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
+/* Add ID_AA64PFR2_EL1 here when HVF supports it */
DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
--
2.43.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PULL 00/44] target-arm queue
2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
` (43 preceding siblings ...)
2025-09-26 14:08 ` [PULL 44/44] target/arm: Implement ID_AA64PFR2_EL1 Peter Maydell
@ 2025-09-27 15:42 ` Richard Henderson
44 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2025-09-27 15:42 UTC (permalink / raw)
To: qemu-devel
On 9/26/25 07:08, Peter Maydell wrote:
> Hi; here's an arm pullreq...
>
> thanks
> -- PMM
>
> The following changes since commit 95b9e0d2ade5d633fd13ffba96a54e87c65baf39:
>
> Merge tag 'for-upstream' ofhttps://gitlab.com/bonzini/qemu into staging (2025-09-24 12:04:18 -0700)
>
> are available in the Git repository at:
>
> https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250926
>
> for you to fetch changes up to b71e2b281a23aca474e128a8487efb07e29f4019:
>
> target/arm: Implement ID_AA64PFR2_EL1 (2025-09-26 13:43:33 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * reimplement VHE alias register handling
> * replace magic GIC values by proper definitions
> * convert power control DPRINTF() uses to trace events
> * better reset related tracepoints
> * implement ID_AA64PFR2_EL1
> * hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint
> * net/passt: Fix build failure due to missing GIO dependency
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
r~
^ permalink raw reply [flat|nested] 48+ messages in thread
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2025-09-26 14:08 [PULL 00/44] target-arm queue Peter Maydell
2025-09-26 14:08 ` [PULL 01/44] hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint Peter Maydell
2025-09-26 14:08 ` [PULL 02/44] net/passt: Fix build failure due to missing GIO dependency Peter Maydell
2025-09-26 14:08 ` [PULL 03/44] target/arm: Introduce KVMID_AA64_SYS_REG64 Peter Maydell
2025-09-26 14:08 ` [PULL 04/44] target/arm: Move compare_u64 to helper.c Peter Maydell
2025-09-26 14:08 ` [PULL 05/44] target/arm/hvf: Split out sysreg.c.inc Peter Maydell
2025-09-26 14:08 ` [PULL 06/44] target/arm/hvf: Reorder DEF_SYSREG arguments Peter Maydell
2025-09-26 14:08 ` [PULL 07/44] target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMID Peter Maydell
2025-09-26 14:08 ` [PULL 08/44] target/arm/hvf: Remove hvf_sreg_match.key Peter Maydell
2025-09-26 14:08 ` [PULL 09/44] target/arm/hvf: Replace hvf_sreg_match with hvf_sreg_list Peter Maydell
2025-09-26 14:08 ` [PULL 10/44] target/arm/hvf: Sort the cpreg_indexes array Peter Maydell
2025-09-26 14:08 ` [PULL 11/44] target/arm/hvf: Use raw_read, raw_write to access Peter Maydell
2025-09-26 14:08 ` [PULL 12/44] target/arm: Use raw_write in cp_reg_reset Peter Maydell
2025-09-26 14:08 ` [PULL 13/44] target/arm: Rename all ARMCPRegInfo from opaque to ri Peter Maydell
2025-09-26 14:08 ` [PULL 14/44] target/arm: Drop define_one_arm_cp_reg_with_opaque Peter Maydell
2025-09-26 14:08 ` [PULL 15/44] target/arm: Restrict the scope of CPREG_FIELD32, CPREG_FIELD64 Peter Maydell
2025-09-26 14:08 ` [PULL 16/44] target/arm: Replace cpreg_field_is_64bit with cpreg_field_type Peter Maydell
2025-09-26 14:08 ` [PULL 17/44] target/arm: Add CP_REG_AA32_64BIT_{SHIFT,MASK} Peter Maydell
2025-09-26 14:08 ` [PULL 18/44] target/arm: Rename CP_REG_AA32_NS_{SHIFT,MASK} Peter Maydell
2025-09-26 14:08 ` [PULL 19/44] target/arm: Convert init_cpreg_list to g_hash_table_foreach Peter Maydell
2025-09-26 14:08 ` [PULL 20/44] target/arm: Remove cp argument to ENCODE_AA64_CP_REG Peter Maydell
2025-09-26 14:08 ` [PULL 21/44] target/arm: Reorder ENCODE_AA64_CP_REG arguments Peter Maydell
2025-09-26 14:08 ` [PULL 22/44] target/arm: Split out add_cpreg_to_hashtable_aa{32, 64} Peter Maydell
2025-09-26 14:08 ` [PULL 23/44] target/arm: Improve asserts in define_one_arm_cp_reg Peter Maydell
2025-09-26 14:08 ` [PULL 24/44] target/arm: Move cp processing to define_one_arm_cp_reg Peter Maydell
2025-09-26 14:08 ` [PULL 25/44] target/arm: Move cpreg elimination " Peter Maydell
2025-09-26 14:08 ` [PULL 26/44] target/arm: Add key parameter to add_cpreg_to_hashtable Peter Maydell
2025-09-26 14:08 ` [PULL 27/44] target/arm: Split out alloc_cpreg Peter Maydell
2025-09-26 14:08 ` [PULL 28/44] target/arm: Hoist the allocation of ARMCPRegInfo Peter Maydell
2025-09-26 14:08 ` [PULL 29/44] target/arm: Remove name argument to alloc_cpreg Peter Maydell
2025-09-26 14:08 ` [PULL 30/44] target/arm: Move alias setting for wildcards Peter Maydell
2025-09-26 14:08 ` [PULL 31/44] target/arm: Move writeback of CP_ANY fields Peter Maydell
2025-09-26 14:08 ` [PULL 32/44] target/arm: Move endianness fixup for 32-bit registers Peter Maydell
2025-09-26 14:08 ` [PULL 33/44] target/arm: Rename TBFLAG_A64_NV2_MEM_E20 with *_E2H Peter Maydell
2025-09-26 14:08 ` [PULL 34/44] target/arm: Split out redirect_cpreg Peter Maydell
2025-09-26 14:08 ` [PULL 35/44] target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation Peter Maydell
2025-09-26 14:08 ` [PULL 36/44] target/arm: Redirect VHE FOO_EL12 to FOO_EL1 " Peter Maydell
2025-09-26 14:08 ` [PULL 37/44] target/arm: Rename some cpreg to their aarch64 names Peter Maydell
2025-09-26 14:08 ` [PULL 38/44] target/arm: Remove define_arm_vh_e2h_redirects_aliases Peter Maydell
2025-09-26 14:08 ` [PULL 39/44] target/arm: Replace magic GIC values by proper definitions Peter Maydell
2025-09-26 14:08 ` [PULL 40/44] target/arm: Convert power control DPRINTF() uses to trace events Peter Maydell
2025-09-26 14:08 ` [PULL 41/44] target/arm: Trace emulated firmware reset call Peter Maydell
2025-09-26 14:08 ` [PULL 42/44] target/arm: Trace vCPU " Peter Maydell
2025-09-26 14:08 ` [PULL 43/44] target/arm: Move ID register field defs to cpu-features.h Peter Maydell
2025-09-26 14:08 ` [PULL 44/44] target/arm: Implement ID_AA64PFR2_EL1 Peter Maydell
2025-09-27 15:42 ` [PULL 00/44] target-arm queue Richard Henderson
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2021-08-25 10:34 Peter Maydell
2021-08-25 17:49 ` Peter Maydell
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