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References: <cover.1542321076.git.alistair.francis@wdc.com>
	<1d5f88588063393fe28b689ce9501715022052ed.1542321076.git.alistair.francis@wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <922cee1e-1f34-d351-75f1-b171b7ef4576@linaro.org>
Date: Fri, 16 Nov 2018 09:13:38 +0100
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Subject: Re: [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for
 the constraints
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To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>

On 11/15/18 11:35 PM, Alistair Francis wrote:
> +    case 'L':
> +        /* qemu_ld/qemu_st constraint */
> +        ct->ct |= TCG_CT_REG;
> +        ct->u.regs = 0xffffffff;
> +        /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
> +#if defined(CONFIG_SOFTMMU)
> +        /* tcg_out_tlb_load uses TCG_REG_TMP0/TMP1 and TCG_REG_L0/L1 */
> +        /* tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP0); */
> +        /* tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP1); */
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP2);

Normally TMP registers are reserved and do not need to be mentioned in
constraints at all.

> +    if ((ct & TCG_CT_CONST_S12) && val >= -2048 && val <= 2047) {
> +        return 1;
> +    }
> +    if ((ct & TCG_CT_CONST_N12) && val >= -2047 && val <= 2048) {
> +        return 1;
> +    }

Clearer as val == sextracttl(val, 0, 12)
and -val == sextracttl(-val, 0, 12)?


r~