From: Richard Henderson <richard.henderson@linaro.org>
To: "Víctor Colombo" <victor.colombo@eldorado.org.br>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com
Subject: Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
Date: Fri, 10 Jun 2022 11:11:13 -0700 [thread overview]
Message-ID: <929ec347-a0eb-44bb-dd75-77944010a828@linaro.org> (raw)
In-Reply-To: <20220610165517.47517-1-victor.colombo@eldorado.org.br>
On 6/10/22 09:55, Víctor Colombo wrote:
> Commit 57c108b8646 introduced gen_set_gpri(), which already contains
> a check for if the destination register is 'zero'. The check in auipc
> and lui are then redundant. This patch removes those checks.
>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2022-06-10 18:12 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 16:55 [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui Víctor Colombo
2022-06-10 18:11 ` Richard Henderson [this message]
2022-06-12 23:37 ` Alistair Francis
2022-06-13 0:28 ` Alistair Francis
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