* [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
@ 2022-06-10 16:55 Víctor Colombo
2022-06-10 18:11 ` Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Víctor Colombo @ 2022-06-10 16:55 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, alistair.francis, bin.meng, richard.henderson,
victor.colombo
Commit 57c108b8646 introduced gen_set_gpri(), which already contains
a check for if the destination register is 'zero'. The check in auipc
and lui are then redundant. This patch removes those checks.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index f1342f30f8..c190a59f22 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -32,17 +32,13 @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
- if (a->rd != 0) {
- gen_set_gpri(ctx, a->rd, a->imm);
- }
+ gen_set_gpri(ctx, a->rd, a->imm);
return true;
}
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
- if (a->rd != 0) {
- gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
- }
+ gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
return true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
2022-06-10 16:55 [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui Víctor Colombo
@ 2022-06-10 18:11 ` Richard Henderson
2022-06-12 23:37 ` Alistair Francis
2022-06-13 0:28 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2022-06-10 18:11 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-riscv
Cc: palmer, alistair.francis, bin.meng
On 6/10/22 09:55, Víctor Colombo wrote:
> Commit 57c108b8646 introduced gen_set_gpri(), which already contains
> a check for if the destination register is 'zero'. The check in auipc
> and lui are then redundant. This patch removes those checks.
>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
2022-06-10 16:55 [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui Víctor Colombo
2022-06-10 18:11 ` Richard Henderson
@ 2022-06-12 23:37 ` Alistair Francis
2022-06-13 0:28 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-06-12 23:37 UTC (permalink / raw)
To: Víctor Colombo
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Bin Meng, Richard Henderson
On Sat, Jun 11, 2022 at 2:59 AM Víctor Colombo
<victor.colombo@eldorado.org.br> wrote:
>
> Commit 57c108b8646 introduced gen_set_gpri(), which already contains
> a check for if the destination register is 'zero'. The check in auipc
> and lui are then redundant. This patch removes those checks.
>
> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index f1342f30f8..c190a59f22 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -32,17 +32,13 @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
>
> static bool trans_lui(DisasContext *ctx, arg_lui *a)
> {
> - if (a->rd != 0) {
> - gen_set_gpri(ctx, a->rd, a->imm);
> - }
> + gen_set_gpri(ctx, a->rd, a->imm);
> return true;
> }
>
> static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
> {
> - if (a->rd != 0) {
> - gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> - }
> + gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> return true;
> }
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
2022-06-10 16:55 [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui Víctor Colombo
2022-06-10 18:11 ` Richard Henderson
2022-06-12 23:37 ` Alistair Francis
@ 2022-06-13 0:28 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-06-13 0:28 UTC (permalink / raw)
To: Víctor Colombo
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Bin Meng, Richard Henderson
On Sat, Jun 11, 2022 at 2:59 AM Víctor Colombo
<victor.colombo@eldorado.org.br> wrote:
>
> Commit 57c108b8646 introduced gen_set_gpri(), which already contains
> a check for if the destination register is 'zero'. The check in auipc
> and lui are then redundant. This patch removes those checks.
>
> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index f1342f30f8..c190a59f22 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -32,17 +32,13 @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
>
> static bool trans_lui(DisasContext *ctx, arg_lui *a)
> {
> - if (a->rd != 0) {
> - gen_set_gpri(ctx, a->rd, a->imm);
> - }
> + gen_set_gpri(ctx, a->rd, a->imm);
> return true;
> }
>
> static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
> {
> - if (a->rd != 0) {
> - gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> - }
> + gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> return true;
> }
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-06-10 16:55 [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui Víctor Colombo
2022-06-10 18:11 ` Richard Henderson
2022-06-12 23:37 ` Alistair Francis
2022-06-13 0:28 ` Alistair Francis
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