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([2602:47:d49d:ec01:3b6c:3864:9643:140a]) by smtp.gmail.com with ESMTPSA id o39-20020a17090a0a2a00b001f262f6f717sm4835655pjo.3.2022.10.07.08.27.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Oct 2022 08:27:51 -0700 (PDT) Message-ID: <92b19bab-1115-cbd2-40e9-45deaa14e857@linaro.org> Date: Fri, 7 Oct 2022 08:27:49 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20221001162318.153420-1-richard.henderson@linaro.org> <20221001162318.153420-28-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.699, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/7/22 02:01, Peter Maydell wrote: > The upcoming v8R support has its stage 2 attributes in the MAIR > format, so it might be a little awkward to assume the v8A-stage-2 > format here rather than being able to add the "if !is_s2_format" > condition. I guess we'll deal with that when we get to it... Ah. I had wondered whether it would be better to convert the result here, so that we always have the MAIR format. I decided against it within the scope of this patch set because it meant that I kept the existing s1+s2 attribute merging logic unchanged. >> + /* >> + * Allow S1_ptw_translate to see any fault generated here. >> + * Since this may recurse, read and clear. >> + */ >> + fi = cpu->env.tlb_fi; >> + if (fi) { >> + cpu->env.tlb_fi = NULL; >> + } else { >> + fi = memset(&local_fi, 0, sizeof(local_fi)); >> + } > > This makes two architectures now that want to do "call a probe_access > function, and get information that's known in the architecture-specific > tlb_fill function", and need to do it via this awkward "have tlb_fill > know that it should stash the info away in the CPU state struct somewhere" > trick (the other being s390 tlb_fill_exc/tlb_fill_tec). But I don't > really have a better idea... A better idea would be most welcome, if anyone has one... :-) r~