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From: WANG Xuerui <i.qemu@xen0n.name>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Laurent Vivier" <laurent@vivier.eu>
Subject: Re: [PATCH v3 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi
Date: Thu, 23 Sep 2021 23:38:38 +0800	[thread overview]
Message-ID: <92b56526-a7ea-7bb3-fecf-10ecfb11a183@xen0n.name> (raw)
In-Reply-To: <08290515-e717-714e-b0cd-f8284a47313a@linaro.org>

Hi Richard,

On 9/23/21 02:51, Richard Henderson wrote:
> On 9/22/21 11:09 AM, WANG Xuerui wrote:
>> +    if (sextreg(val, 0, 52) == val) {
>> +        /*
>> +         * Fits in 52-bits, upper bits are already properly 
>> sign-extended by
>> +         * cu32i.d.
>> +         */
>> +        return;
>> +    }
>> +    tcg_out_opc_cu52i_d(s, rd, rd, top);
>> +}
>
> Oh, future improvement: constants with 52 low zero bits can be loaded 
> with cu52i(rd, zero, val >> 52).
>
> Which means there's a set of interesting constants:
>
>   abc0_0000_0000_0def
>
>     ori    rd, zero, 0xdef
>     cu52i    rd, rd, 0xabc
>
>   abcf_ffff_ffff_fdef
>
>     cu52i    rd, zero, 0xabc - 1
>     addi.d    rd, rd, 0xdef
I think I'll try to implement this in some kind of follow-up patch, yeah.
>
> Also,
>
>> +    tcg_out_opc_lu12i_w(s, rd, upper);
>> +    if (low != 0) {
>> +        tcg_out_opc_ori(s, rd, rd, low & 0xfff);
>> +    }
>
> when upper == 0 and low != 0, we can omit the lu12i.
>
This optimization can't be blindly implemented though; because cu32i.d 
only takes one input register, in case upper == low == 0 but higher != 
0, we would have no proper input. So in that case something like "move 
rd, zero" is necessary, and logic is a little bit complicated. I'll 
include this in v4 though.
>
> r~


  reply	other threads:[~2021-09-23 15:42 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-22 18:08 [PATCH v3 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-22 18:08 ` [PATCH v3 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-22 18:17   ` Richard Henderson
2021-09-22 18:23   ` Philippe Mathieu-Daudé
2021-09-22 18:08 ` [PATCH v3 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-22 18:34   ` Philippe Mathieu-Daudé
2021-09-22 18:47     ` WANG Xuerui
2021-09-22 18:58     ` Richard Henderson
2021-09-23 10:35       ` Philippe Mathieu-Daudé
2021-09-22 18:09 ` [PATCH v3 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-22 18:37   ` Philippe Mathieu-Daudé
2021-09-22 18:51     ` WANG Xuerui
2021-09-22 19:32       ` Philippe Mathieu-Daudé
2021-09-22 18:09 ` [PATCH v3 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 06/30] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-22 18:41   ` Philippe Mathieu-Daudé
2021-09-22 18:55     ` WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-22 18:39   ` Richard Henderson
2021-09-22 19:02     ` WANG Xuerui
2021-09-22 18:51   ` Richard Henderson
2021-09-23 15:38     ` WANG Xuerui [this message]
2021-09-23 16:50   ` Richard Henderson
2021-09-24 15:08     ` WANG Xuerui
2021-09-24 15:53       ` Richard Henderson
2021-09-24 16:26         ` WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-09-22 18:23   ` Richard Henderson
2021-09-22 18:09 ` [PATCH v3 15/30] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-22 18:25   ` Richard Henderson
2021-09-22 18:09 ` [PATCH v3 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-23 17:25   ` Richard Henderson
2021-09-22 18:09 ` [PATCH v3 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 27/30] tcg/loongarch64: Register the JIT WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 30/30] configure, meson.build: Mark support " WANG Xuerui

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