Re: [Qemu-devel] [PATCH 7/8] target/ppc: Optimize emulation of vclzh and vclzb instructions

[Richard Henderson <richard.henderson@linaro.org>]

On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> Optimize Altivec instruction vclzh (Vector Count Leading Zeros Halfword).
> This instruction counts the number of leading zeros of each halfword element
> in source register and places result in the appropriate halfword element of
> destination register.
For halfword, you're generating 32 operations.  A loop over the halfwords,
similar to the word loop I suggested for the last patch, does not reduce this
total, since one has to adjust the clz32 result.

For byte, you're generating 64 operations.

These expansions are so big that without host vector support it's probably best
to leave them out-of-line.

I can imagine a byte clz expansion like

	t0 = input >> 4;
	t1 = input << 4;
	cmp = input == 0 ? -1 : 0;
	input = cmp ? t1 : input;
	output = cmp & 4;

	t0 = input >> 6;
	t1 = input << 2;
	cmp = input == 0 ? -1 : 0;
	input = cmp ? t1 : input;
	t0 = cmp & 2;
	output += t0;

	t1 = input << 1;
	cmp = input >= 0 ? -1 : 0;
	output -= cmp;

	cmp = input == 0 ? -1 : 0;
	output -= cmp;

which would expand to 20 x86_64 vector instructions.  A halfword expansion
would require one more round and thus 25 instructions.

I'll also note that ARM, Power8, and S390 all support this as a native vector
operation; only x86_64 would require the above expansion.  It probably makes
sense to add this operation to tcg.


r~