From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: Re: [PATCH v2 5/8] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs
Date: Wed, 12 Feb 2025 10:10:30 -0800 [thread overview]
Message-ID: <932bd6db-0b65-4a24-9095-1fde1b7f673a@linaro.org> (raw)
In-Reply-To: <20250212154333.28644-6-philmd@linaro.org>
On 2/12/25 07:43, Philippe Mathieu-Daudé wrote:
> Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14)
> on Appendix A: Register Details, the mpcore Interrupt Controller Type
> Register (ICDICTR) has the IT_Lines_Number field read-only with value
> 0x2, described as:
>
> IT_Lines_Number
>
> b00010 = the distributor provides 96 interrupts,
> 64 external interrupt lines.
>
> Add a GIC_EXT_IRQS definition (with a comment) to make the number of
> GIC external IRQs explicit.
>
> Except explicitly setting a property value to its same implicit
> value, there is no logical change intended.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> hw/arm/xilinx_zynq.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2025-02-12 18:11 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-12 15:43 [PATCH v2 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore Philippe Mathieu-Daudé
2025-02-12 15:43 ` [PATCH v2 1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Philippe Mathieu-Daudé
2025-02-12 17:57 ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 2/8] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Philippe Mathieu-Daudé
2025-02-12 17:59 ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 3/8] hw/arm/realview: " Philippe Mathieu-Daudé
2025-02-12 18:01 ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Philippe Mathieu-Daudé
2025-02-12 18:02 ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 5/8] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Philippe Mathieu-Daudé
2025-02-12 18:10 ` Richard Henderson [this message]
2025-02-12 15:43 ` [PATCH v2 6/8] hw/arm/vexpress: " Philippe Mathieu-Daudé
2025-02-12 18:12 ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 7/8] hw/arm/highbank: Specify explicitly the GIC has 128 " Philippe Mathieu-Daudé
2025-02-12 18:12 ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 8/8] hw/cpu/arm_mpcore: Remove default values for GIC " Philippe Mathieu-Daudé
2025-02-12 18:13 ` Richard Henderson
2025-02-17 15:43 ` [PATCH v2 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore Peter Maydell
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