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From: Sebastian Huber <sebastian.huber@embedded-brains.de>
To: qemu-devel <qemu-devel@nongnu.org>
Cc: qemu-arm <qemu-arm@nongnu.org>
Subject: Re: Xilinx Zynq 7000 Start of CPU1
Date: Thu, 19 Sep 2024 02:28:50 +0200 (CEST)	[thread overview]
Message-ID: <934066607.108860.1726705730827.JavaMail.zimbra@embedded-brains.de> (raw)
In-Reply-To: <1242128488.101916.1726650812387.JavaMail.zimbra@embedded-brains.de>

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----- Am 18. Sep 2024 um 11:13 schrieb Sebastian Huber sebastian.huber@embedded-brains.de:

> Hello,
> 
> I recently added the support for CPU1 to the xilinx-zynq-a9 machine
> (hw/arm/xilinx_zynq.c). However, the reset behaviour doesn't match exactly with
> the hardware. After a system reset (SRST), the CPU1 should execute a wfe
> instruction and then load the start address from 0xfffffff0:
> 
> https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1
> 
> It would be great if someone has a hint for me how I can add this startup code
> for CPU1 at address region 0xFFFFFE00 to 0xFFFFFFF0.

I got it working with some hacks in arm_load_kernel() and do_cpu_reset(). In arm_load_kernel() had to remove the:

        /*
         * No secondary boot stub; don't use the reset hook that would
         * have set the CPU up to call it
         */
        info->write_secondary_boot = NULL;
        info->secondary_cpu_reset_hook = NULL;

This change probably breaks a lot of things. I am not sure how to address this issue.

-- 
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      reply	other threads:[~2024-09-19  0:29 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-18  9:13 Xilinx Zynq 7000 Start of CPU1 Sebastian Huber
2024-09-19  0:28 ` Sebastian Huber [this message]

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