From: Thomas Huth <thuth@redhat.com>
To: zhaolichang <zhaolichang@huawei.com>, qemu-trivial@nongnu.org
Cc: David Edmondson <david.edmondson@oracle.com>,
qemu-s390x <qemu-s390x@nongnu.org>,
qemu-devel@nongnu.org
Subject: Re: [PATCH V2 07/14] s390x/: fix some comment spelling errors
Date: Fri, 9 Oct 2020 09:31:14 +0200 [thread overview]
Message-ID: <937308f7-a861-0930-4fd1-ecf815463012@redhat.com> (raw)
In-Reply-To: <20201009064449.2336-8-zhaolichang@huawei.com>
On 09/10/2020 08.44, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/s390x.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
> Reviewed-by: David Edmondson <david.edmondson@oracle.com>
> ---
> target/s390x/cpu_models.h | 4 ++--
> target/s390x/excp_helper.c | 2 +-
> target/s390x/fpu_helper.c | 2 +-
> target/s390x/insn-data.def | 2 +-
> target/s390x/misc_helper.c | 2 +-
> target/s390x/translate.c | 4 ++--
> target/s390x/translate_vx.c.inc | 2 +-
> 7 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h
> index 74d1f87e4f..15c0f0dcfe 100644
> --- a/target/s390x/cpu_models.h
> +++ b/target/s390x/cpu_models.h
> @@ -24,13 +24,13 @@ struct S390CPUDef {
> uint8_t gen; /* hw generation identification */
> uint16_t type; /* cpu type identification */
> uint8_t ec_ga; /* EC GA version (on which also the BC is based) */
> - uint8_t mha_pow; /* Maximum Host Adress Power, mha = 2^pow-1 */
> + uint8_t mha_pow; /* Maximum Host Address Power, mha = 2^pow-1 */
> uint32_t hmfai; /* hypervisor-managed facilities */
> /* base/min features, must never be changed between QEMU versions */
> S390FeatBitmap base_feat;
> /* used to init base_feat from generated data */
> S390FeatInit base_init;
> - /* deafault features, QEMU version specific */
> + /* default features, QEMU version specific */
> S390FeatBitmap default_feat;
> /* used to init default_feat from generated data */
> S390FeatInit default_init;
> diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
> index 0adfbbda27..36ab5c7c43 100644
> --- a/target/s390x/excp_helper.c
> +++ b/target/s390x/excp_helper.c
> @@ -538,7 +538,7 @@ try_deliver:
> /* don't trigger a cpu_loop_exit(), use an interrupt instead */
> cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HALT);
> } else if (cs->halted) {
> - /* unhalt if we had a WAIT PSW somehwere in our injection chain */
> + /* unhalt if we had a WAIT PSW somewhere in our injection chain */
> s390_cpu_unhalt(cpu);
> }
> }
> diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c
> index f155bc048c..3e609b7fd0 100644
> --- a/target/s390x/fpu_helper.c
> +++ b/target/s390x/fpu_helper.c
> @@ -89,7 +89,7 @@ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr)
> /*
> * invalid/divbyzero cannot coexist with other conditions.
> * overflow/underflow however can coexist with inexact, we have to
> - * handle it separatly.
> + * handle it separately.
> */
> if (s390_exc & ~S390_IEEE_MASK_INEXACT) {
> if (s390_exc & ~S390_IEEE_MASK_INEXACT & env->fpc >> 24) {
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index d3bcdfd67b..2469415319 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -526,7 +526,7 @@
> /* LOAD LOGICAL HALFWORD RELATIVE LONG */
> C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0)
> C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0)
> -/* LOAD LOGICAL IMMEDATE */
> +/* LOAD LOGICAL IMMEDIATE */
> D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32)
> D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0)
> D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48)
> diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
> index 58dbc023eb..929e509519 100644
> --- a/target/s390x/misc_helper.c
> +++ b/target/s390x/misc_helper.c
> @@ -312,7 +312,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1)
> /* same as machine type number in STORE CPU ID, but in EBCDIC */
> snprintf(type, ARRAY_SIZE(type), "%X", cpu->model->def->type);
> ebcdic_put(sysib.sysib_111.type, type, 4);
> - /* model number (not stored in STORE CPU ID for z/Architecure) */
> + /* model number (not stored in STORE CPU ID for z/Architecture) */
> ebcdic_put(sysib.sysib_111.model, "QEMU ", 16);
> ebcdic_put(sysib.sysib_111.sequence, "QEMU ", 16);
> ebcdic_put(sysib.sysib_111.plant, "QEMU", 4);
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index ac10f42f10..4395455e0a 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -433,7 +433,7 @@ static void gen_program_exception(DisasContext *s, int code)
> {
> TCGv_i32 tmp;
>
> - /* Remember what pgm exeption this was. */
> + /* Remember what pgm exception this was. */
> tmp = tcg_const_i32(code);
> tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
> tcg_temp_free_i32(tmp);
> @@ -489,7 +489,7 @@ static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
>
> /*
> * Note that d2 is limited to 20 bits, signed. If we crop negative
> - * displacements early we create larger immedate addends.
> + * displacements early we create larger immediate addends.
> */
> if (b2 && x2) {
> tcg_gen_add_i64(tmp, regs[b2], regs[x2]);
> diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
> index eb767f5288..983da56b9d 100644
> --- a/target/s390x/translate_vx.c.inc
> +++ b/target/s390x/translate_vx.c.inc
> @@ -789,7 +789,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
> }
> break;
> case 0x94:
> - /* If sources and destination dont't overlap -> fast path */
> + /* If sources and destination don't overlap -> fast path */
> if (v1 != v2 && v1 != v3) {
> const uint8_t src_es = get_field(s, m4);
> const uint8_t dst_es = src_es - 1;
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
next prev parent reply other threads:[~2020-10-09 7:32 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-09 6:44 [PATCH V2 00/14] fix some comment spelling errors zhaolichang
2020-10-09 6:44 ` [PATCH V2 01/14] cris/: " zhaolichang
2020-10-09 13:14 ` Eric Blake
2020-10-09 6:44 ` [PATCH V2 02/14] ppc/: " zhaolichang
2020-10-26 9:14 ` Thomas Huth
2020-10-26 10:04 ` Greg Kurz
2020-10-27 2:05 ` David Gibson
2020-10-27 2:07 ` David Gibson
2020-10-09 6:44 ` [PATCH V2 03/14] riscv/: " zhaolichang
2020-10-09 7:15 ` Bin Meng
2020-10-09 6:44 ` [PATCH V2 04/14] rx/: " zhaolichang
2020-10-26 22:14 ` Philippe Mathieu-Daudé
2020-10-09 6:44 ` [PATCH V2 05/14] tricore/: " zhaolichang
2020-10-09 6:44 ` [PATCH V2 06/14] mips/: " zhaolichang
2020-10-09 14:36 ` Philippe Mathieu-Daudé
2020-10-09 15:15 ` Philippe Mathieu-Daudé
2020-10-09 6:44 ` [PATCH V2 07/14] s390x/: " zhaolichang
2020-10-09 7:31 ` Thomas Huth [this message]
2020-10-09 6:44 ` [PATCH V2 08/14] m68k/: " zhaolichang
2020-12-12 17:10 ` Laurent Vivier
2020-12-12 17:56 ` Philippe Mathieu-Daudé
2020-12-12 19:58 ` Laurent Vivier
2020-12-12 20:04 ` Philippe Mathieu-Daudé
2020-10-09 6:44 ` [PATCH V2 09/14] sh4/: " zhaolichang
2020-10-25 0:37 ` Philippe Mathieu-Daudé
2020-10-09 6:44 ` [PATCH V2 10/14] i386/: " zhaolichang
2020-10-09 6:44 ` [PATCH V2 11/14] avr/: " zhaolichang
2020-10-09 6:44 ` [PATCH V2 12/14] arm/: " zhaolichang
2020-10-09 6:44 ` [PATCH V2 13/14] alpha/: " zhaolichang
2020-10-09 6:44 ` [PATCH V2 14/14] target/: " zhaolichang
2020-10-09 7:12 ` [PATCH V2 00/14] " no-reply
[not found] ` <a5a68476-0ed8-08f9-f993-464317d798bf@huawei.com>
2020-10-20 6:42 ` Philippe Mathieu-Daudé
2020-10-29 2:22 ` Lichang Zhao
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