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Sun, 11 Dec 2022 18:28:13 GMT Received: from smtpav01.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CDD2D5804B; Sun, 11 Dec 2022 18:28:13 +0000 (GMT) Received: from smtpav01.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C6CFE58068; Sun, 11 Dec 2022 18:28:09 +0000 (GMT) Received: from [9.43.104.144] (unknown [9.43.104.144]) by smtpav01.wdc07v.mail.ibm.com (Postfix) with ESMTP; Sun, 11 Dec 2022 18:28:09 +0000 (GMT) Message-ID: <93d6b1dd-54a9-ec82-10c5-6261ffcda91a@linux.ibm.com> Date: Sun, 11 Dec 2022 23:58:07 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v2 1/2] target/ppc: Implement the DEXCR and HDEXCR To: Nicholas Miehlbradt , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, clg@kaod.org, david@gibson.dropbear.id.au, groug@kaod.org, victor.colombo@eldorado.org.br, mikey@neuling.org References: <20221209061308.1735802-1-nicholas@linux.ibm.com> <20221209061308.1735802-2-nicholas@linux.ibm.com> Content-Language: en-US From: Harsh Prateek Bora In-Reply-To: <20221209061308.1735802-2-nicholas@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: _6oSvWNKJ4NORVajzaqJoR4V-QbMF9ip X-Proofpoint-GUID: kDrholIaCDiWIk56wwffnnn_wloLKe8L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-10_10,2022-12-08_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 mlxlogscore=999 clxscore=1011 priorityscore=1501 malwarescore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212110169 Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 11 Dec 2022 13:58:41 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/9/22 11:43, Nicholas Miehlbradt wrote: > Define the DEXCR and HDEXCR as special purpose registers. > > Each register occupies two SPR indicies, one which can be read in an > unprivileged state and one which can be modified in the appropriate > priviliged state, however both indicies refer to the same underlying > value. > > Note that the ISA uses the abbreviation UDEXCR in two different > contexts: the userspace DEXCR, the SPR index which can be read from > userspace (implemented in this patch), and the ultravisor DEXCR, the > equivalent register for the ultravisor state (not implemented). > > Signed-off-by: Nicholas Miehlbradt > --- > v2: Clearing of upper 32 bits of DEXCR is now performed on read from > problem state rather than on write in privileged state. > --- > target/ppc/cpu.h | 19 +++++++++++++++++++ > target/ppc/cpu_init.c | 25 +++++++++++++++++++++++++ > target/ppc/spr_common.h | 1 + > target/ppc/translate.c | 19 +++++++++++++++++++ > 4 files changed, 64 insertions(+) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 81d4263a07..0ed9f2ae35 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1068,6 +1068,21 @@ struct ppc_radix_page_info { > uint32_t entries[PPC_PAGE_SIZES_MAX_SZ]; > }; > > +/*****************************************************************************/ > +/* Dynamic Execution Control Register */ > + > +#define DEXCR_ASPECT(name, num) \ > +FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1) \ > +FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1) \ > +FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1) \ > +FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \ > + > +DEXCR_ASPECT(SBHE, 0) > +DEXCR_ASPECT(IDRTPB, 1) ^^^^^^ IBRTPD ? > +DEXCR_ASPECT(SRAPD, 4) > +DEXCR_ASPECT(NPHIE, 5) > +DEXCR_ASPECT(PHIE, 6) > + > /*****************************************************************************/ > /* The whole PowerPC CPU context */ > > @@ -1674,9 +1689,11 @@ void ppc_compat_add_property(Object *obj, const char *name, > #define SPR_BOOKE_GIVOR13 (0x1BC) > #define SPR_BOOKE_GIVOR14 (0x1BD) > #define SPR_TIR (0x1BE) > +#define SPR_UHDEXCR (0x1C7) > #define SPR_PTCR (0x1D0) > #define SPR_HASHKEYR (0x1D4) > #define SPR_HASHPKEYR (0x1D5) > +#define SPR_HDEXCR (0x1D7) > #define SPR_BOOKE_SPEFSCR (0x200) > #define SPR_Exxx_BBEAR (0x201) > #define SPR_Exxx_BBTAR (0x202) > @@ -1865,8 +1882,10 @@ void ppc_compat_add_property(Object *obj, const char *name, > #define SPR_RCPU_L2U_RA2 (0x32A) > #define SPR_MPC_MD_DBRAM1 (0x32A) > #define SPR_RCPU_L2U_RA3 (0x32B) > +#define SPR_UDEXCR (0x32C) > #define SPR_TAR (0x32F) > #define SPR_ASDR (0x330) > +#define SPR_DEXCR (0x33C) > #define SPR_IC (0x350) > #define SPR_VTB (0x351) > #define SPR_MMCRC (0x353) > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index cbf0081374..6433f4fdfd 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -5727,6 +5727,30 @@ static void register_power10_hash_sprs(CPUPPCState *env) > hashpkeyr_initial_value); > } > > +static void register_power10_dexcr_sprs(CPUPPCState *env) > +{ > + spr_register(env, SPR_DEXCR, "DEXCR", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0); > + > + spr_register(env, SPR_UDEXCR, "DEXCR", > + &spr_read_dexcr_ureg, SPR_NOACCESS, > + &spr_read_dexcr_ureg, SPR_NOACCESS, > + 0); > + > + spr_register_hv(env, SPR_HDEXCR, "HDEXCR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0); > + > + spr_register(env, SPR_UHDEXCR, "HDEXCR", > + &spr_read_dexcr_ureg, SPR_NOACCESS, > + &spr_read_dexcr_ureg, SPR_NOACCESS, > + 0); > +} > + > /* > * Initialize PMU counter overflow timers for Power8 and > * newer Power chips when using TCG. > @@ -6402,6 +6426,7 @@ static void init_proc_POWER10(CPUPPCState *env) > register_power8_rpr_sprs(env); > register_power9_mmu_sprs(env); > register_power10_hash_sprs(env); > + register_power10_dexcr_sprs(env); > > /* FIXME: Filter fields properly based on privilege level */ > spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, > diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h > index b5a5bc6895..91a74cec0f 100644 > --- a/target/ppc/spr_common.h > +++ b/target/ppc/spr_common.h > @@ -195,6 +195,7 @@ void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn); > void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn); > void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); > void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); > +void spr_read_dexcr_ureg(DisasContext *ctx, int sprn, int gprn); Order of sprn, gprn appears different in funcn defn below, need to correct at either place. > #endif > > void register_low_BATs(CPUPPCState *env); > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 19c1d17cb0..fcb1180712 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -1249,6 +1249,25 @@ void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) > gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); > spr_write_prev_upper32(ctx, sprn, gprn); > } > + > +void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) > +{ > + TCGv t0 = tcg_temp_new(); > + > + /* > + * Access to the (H)DEXCR in problem state is done using seperate > + * SPR indexes which are 16 below the SPR indexes which have full > + * access to the (H)DEXCR in privileged state. Problem state may s/may/can ? > + * only read bits 32:63, bits 0:31 return 0. > + * > + * See section 9.3.1-9.3.2 of PowerISA v3.1B > + */ > + > + gen_load_spr(t0, sprn + 16); > + tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); > + > + tcg_temp_free(t0); > +} > #endif > > #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ Otherwise, looks good to me!