From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:51880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TP6Gm-00045m-C2 for qemu-devel@nongnu.org; Fri, 19 Oct 2012 02:41:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TP6Gk-00040H-PM for qemu-devel@nongnu.org; Fri, 19 Oct 2012 02:41:20 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:49217) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TP6Gk-0003w6-Ja for qemu-devel@nongnu.org; Fri, 19 Oct 2012 02:41:18 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so88083dad.4 for ; Thu, 18 Oct 2012 23:41:18 -0700 (PDT) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Fri, 19 Oct 2012 16:40:30 +1000 Message-Id: <93e240df797a15adf80de85faa1325eb6bdd6c1b.1350619775.git.peter.crosthwaite@xilinx.com> In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [PATCH v1 6/7] xilinx_zynq: add pl353 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com, peter.maydell@linaro.org Cc: Peter Crosthwaite , john.williams@xilinx.com Add the pl353 memory controller with both NAND and parallel flashes attached. Signed-off-by: Peter Crosthwaite --- hw/xilinx_zynq.c | 49 +++++++++++++++++++++++++++++++++++++++++-------- 1 files changed, 41 insertions(+), 8 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index fd46ba2..7f6faf0 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -120,14 +120,47 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, vmstate_register_ram_global(ocm_ram); memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); - DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); - - /* AMD */ - pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, - dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE, - FLASH_SIZE/FLASH_SECTOR_SIZE, 1, - 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, - 0); + /* pl353 */ + dev = qdev_create(NULL, "arm.pl35x"); + /* FIXME: handle this somewhere central */ + object_property_add_child(container_get(qdev_get_machine(), "/unattached"), + "pl353", OBJECT(dev), NULL); + qdev_prop_set_uint8(dev, "x", 3); + { + DriveInfo *dinfo = drive_get_next(IF_PFLASH); + BlockDriverState *bs = dinfo ? dinfo->bdrv : NULL; + DeviceState *att_dev = qdev_create(NULL, "cfi.pflash02"); + Error *errp = NULL; + + if (bs && qdev_prop_set_drive(att_dev, "bdrv", bs)) { + abort(); + } + qdev_prop_set_uint32(att_dev, "nb_blocs", + FLASH_SIZE/FLASH_SECTOR_SIZE); + qdev_prop_set_uint32(att_dev, "sector_len", FLASH_SECTOR_SIZE); + qdev_prop_set_uint8(att_dev, "width", 1); + qdev_prop_set_uint8(att_dev, "mappings", 1); + qdev_prop_set_uint8(att_dev, "be", 0); + qdev_prop_set_uint16(att_dev, "id0", 0x0066); + qdev_prop_set_uint16(att_dev, "id1", 0x0022); + qdev_prop_set_uint16(att_dev, "id2", 0x0000); + qdev_prop_set_uint16(att_dev, "id3", 0x0000); + qdev_prop_set_uint16(att_dev, "unlock_addr0", 0x0aaa); + qdev_prop_set_uint16(att_dev, "unlock_addr1", 0x0555); + qdev_init_nofail(att_dev); + object_property_set_link(OBJECT(dev), OBJECT(att_dev), "dev0", &errp); + assert_no_error(errp); + + dinfo = drive_get_next(IF_PFLASH); + att_dev = nand_init(dinfo ? dinfo->bdrv : NULL, NAND_MFR_STMICRO, 0xaa); + object_property_set_link(OBJECT(dev), OBJECT(att_dev), "dev1", &errp); + assert_no_error(errp); + } + qdev_init_nofail(dev); + busdev = sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, 0xe000e000); + sysbus_mmio_map(busdev, 1, 0xe2000000); + sysbus_mmio_map(busdev, 2, 0xe1000000); dev = qdev_create(NULL, "xilinx,zynq_slcr"); qdev_init_nofail(dev); -- 1.7.0.4