[PATCH v2 0/3] Fix some more RVV source overlap issues

[PATCH v2 0/3] Fix some more RVV source overlap issues

[Max Chou]

This patchset is based on the v1 provided by Anoton Blanchard with
following update:

* Add the missing input EEWs checking rule for widen vector reduction
  instruction.

Reference:
* v1: 20250415043207.3512209-1-antonb@tenstorrent.com

Anton Blanchard (3):
  target/riscv: rvv: Apply vext_check_input_eew to vector integer/fp
    compare instructions
  target/riscv: rvv: Apply vext_check_input_eew to vector reduction
    instructions
  target/riscv: vadc and vsbc are vm=0 instructions

 target/riscv/insn32.decode              | 10 +++++-----
 target/riscv/insn_trans/trans_rvv.c.inc | 26 ++++++++++++++-----------
 2 files changed, 20 insertions(+), 16 deletions(-)

-- 
2.43.0

[PATCH v2 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector integer/fp compare instructions

[Max Chou]

From: Anton Blanchard <antonb@tenstorrent.com>

Handle the overlap of source registers with different EEWs.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2b6077ac067..ec34d0d8c47 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -436,9 +436,10 @@ static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
            require_align(vs1, s->lmul);
 }
 
-static bool vext_check_ms(DisasContext *s, int vd, int vs)
+static bool vext_check_ms(DisasContext *s, int vd, int vs, int vm)
 {
-    bool ret = require_align(vs, s->lmul);
+    bool ret = require_align(vs, s->lmul) &&
+               vext_check_input_eew(s, vs, s->sew, -1, 0, vm);
     if (vd != vs) {
         ret &= require_noover(vd, 0, vs, s->lmul);
     }
@@ -461,9 +462,10 @@ static bool vext_check_ms(DisasContext *s, int vd, int vs)
  *      with a mask value (e.g., comparisons) or the scalar result
  *      of a reduction. (Section 5.3)
  */
-static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
+static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2, int vm)
 {
-    bool ret = vext_check_ms(s, vd, vs2) &&
+    bool ret = vext_check_ms(s, vd, vs2, vm) &&
+               vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
                require_align(vs1, s->lmul);
     if (vd != vs1) {
         ret &= require_noover(vd, 0, vs1, s->lmul);
@@ -2040,7 +2042,7 @@ static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_mss(s, a->rd, a->rs1, a->rs2);
+           vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
 
 GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
@@ -2076,7 +2078,7 @@ static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ms(s, a->rd, a->rs2);
+           vext_check_ms(s, a->rd, a->rs2, a->vm);
 }
 
 GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
@@ -2250,7 +2252,7 @@ static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_mss(s, a->rd, a->rs1, a->rs2);
+           vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
 
 GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
@@ -2264,7 +2266,7 @@ static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ms(s, a->rd, a->rs2);
+           vext_check_ms(s, a->rd, a->rs2, a->vm);
 }
 
 GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
@@ -2972,7 +2974,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_mss(s, a->rd, a->rs1, a->rs2);
+           vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
 
 GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2985,7 +2987,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ms(s, a->rd, a->rs2);
+           vext_check_ms(s, a->rd, a->rs2, a->vm);
 }
 
 GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
-- 
2.43.0

Re: [PATCH v2 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector integer/fp compare instructions

[Nutty Liu]

On 6/27/2025 9:20 PM, Max Chou wrote:
> From: Anton Blanchard <antonb@tenstorrent.com>
>
> Handle the overlap of source registers with different EEWs.
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++----------
>   1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2b6077ac067..ec34d0d8c47 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -436,9 +436,10 @@ static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
>              require_align(vs1, s->lmul);
>   }
>   
> -static bool vext_check_ms(DisasContext *s, int vd, int vs)
> +static bool vext_check_ms(DisasContext *s, int vd, int vs, int vm)
>   {
> -    bool ret = require_align(vs, s->lmul);
> +    bool ret = require_align(vs, s->lmul) &&
> +               vext_check_input_eew(s, vs, s->sew, -1, 0, vm);
>       if (vd != vs) {
>           ret &= require_noover(vd, 0, vs, s->lmul);
>       }
> @@ -461,9 +462,10 @@ static bool vext_check_ms(DisasContext *s, int vd, int vs)
>    *      with a mask value (e.g., comparisons) or the scalar result
>    *      of a reduction. (Section 5.3)
>    */
> -static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
> +static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2, int vm)
>   {
> -    bool ret = vext_check_ms(s, vd, vs2) &&
> +    bool ret = vext_check_ms(s, vd, vs2, vm) &&
> +               vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
>                  require_align(vs1, s->lmul);
>       if (vd != vs1) {
>           ret &= require_noover(vd, 0, vs1, s->lmul);
> @@ -2040,7 +2042,7 @@ static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_mss(s, a->rd, a->rs1, a->rs2);
> +           vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
>   }
>   
>   GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
> @@ -2076,7 +2078,7 @@ static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_ms(s, a->rd, a->rs2);
> +           vext_check_ms(s, a->rd, a->rs2, a->vm);
>   }
>   
>   GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
> @@ -2250,7 +2252,7 @@ static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_mss(s, a->rd, a->rs1, a->rs2);
> +           vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
>   }
>   
>   GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
> @@ -2264,7 +2266,7 @@ static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_ms(s, a->rd, a->rs2);
> +           vext_check_ms(s, a->rd, a->rs2, a->vm);
>   }
>   
>   GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
> @@ -2972,7 +2974,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
>       return require_rvv(s) &&
>              require_rvf(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_mss(s, a->rd, a->rs1, a->rs2);
> +           vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
>   }
>   
>   GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
> @@ -2985,7 +2987,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
>       return require_rvv(s) &&
>              require_rvf(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_ms(s, a->rd, a->rs2);
> +           vext_check_ms(s, a->rd, a->rs2, a->vm);
>   }
>   
>   GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)

Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>

Thanks,
Nutty

[PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions

[Max Chou]

From: Anton Blanchard <antonb@tenstorrent.com>

Handle the overlap of source registers with different EEWs.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ec34d0d8c47..ac6f1d04c6d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3293,6 +3293,7 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
            vext_check_reduction(s, a->rs2);
 }
 
@@ -3309,7 +3310,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
 static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) && (s->sew < MO_64) &&
-           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
+           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
+           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1, a->vm);
 }
 
 GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
-- 
2.43.0

Re: [PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions

[Nutty Liu]

On 6/27/2025 9:20 PM, Max Chou wrote:
> From: Anton Blanchard <antonb@tenstorrent.com>
>
> Handle the overlap of source registers with different EEWs.

Above description is the same as [patch v2 1/3].
They are different functions.
Maybe need to add some different description.

Otherwise,
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>

Thanks,
Nutty

>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index ec34d0d8c47..ac6f1d04c6d 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3293,6 +3293,7 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
>              vext_check_reduction(s, a->rs2);
>   }
>   
> @@ -3309,7 +3310,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
>   static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
>   {
>       return reduction_check(s, a) && (s->sew < MO_64) &&
> -           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
> +           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1, a->vm);
>   }
>   
>   GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)

Re: [PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions

[Max Chou]

[-- Attachment #1: Type: text/plain, Size: 1965 bytes --]

Hi Nutty,

Thanks for the suggestion.
I'll provide a new version including the new description and a fix about
another EEWs issue.

Thanks,
Max


On Tue, Jul 1, 2025 at 2:43 PM Nutty Liu <liujingqi@lanxincomputing.com>
wrote:

> On 6/27/2025 9:20 PM, Max Chou wrote:
> > From: Anton Blanchard <antonb@tenstorrent.com>
> >
> > Handle the overlap of source registers with different EEWs.
>
> Above description is the same as [patch v2 1/3].
> They are different functions.
> Maybe need to add some different description.
>
> Otherwise,
> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
>
> Thanks,
> Nutty
>
> >
> > Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> >   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
> >   1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> > index ec34d0d8c47..ac6f1d04c6d 100644
> > --- a/target/riscv/insn_trans/trans_rvv.c.inc
> > +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> > @@ -3293,6 +3293,7 @@ static bool reduction_check(DisasContext *s,
> arg_rmrr *a)
> >   {
> >       return require_rvv(s) &&
> >              vext_check_isa_ill(s) &&
> > +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew,
> a->vm) &&
> >              vext_check_reduction(s, a->rs2);
> >   }
> >
> > @@ -3309,7 +3310,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
> >   static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
> >   {
> >       return reduction_check(s, a) && (s->sew < MO_64) &&
> > -           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
> > +           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
> > +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1,
> a->vm);
> >   }
> >
> >   GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
>

[-- Attachment #2: Type: text/html, Size: 3120 bytes --]

[PATCH v2 3/3] target/riscv: vadc and vsbc are vm=0 instructions

[Max Chou]

From: Anton Blanchard <antonb@tenstorrent.com>

We were marking vadc and vsbc as vm=1 instructions, which meant
vext_check_input_eew wouldn't detect mask vs source register
overlaps.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn32.decode | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index cd23b1f3a9b..5442203ecaa 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -451,14 +451,14 @@ vwsubu_wv       110110 . ..... ..... 010 ..... 1010111 @r_vm
 vwsubu_wx       110110 . ..... ..... 110 ..... 1010111 @r_vm
 vwsub_wv        110111 . ..... ..... 010 ..... 1010111 @r_vm
 vwsub_wx        110111 . ..... ..... 110 ..... 1010111 @r_vm
-vadc_vvm        010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
-vadc_vxm        010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
-vadc_vim        010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
+vadc_vvm        010000 0 ..... ..... 000 ..... 1010111 @r_vm_0
+vadc_vxm        010000 0 ..... ..... 100 ..... 1010111 @r_vm_0
+vadc_vim        010000 0 ..... ..... 011 ..... 1010111 @r_vm_0
 vmadc_vvm       010001 . ..... ..... 000 ..... 1010111 @r_vm
 vmadc_vxm       010001 . ..... ..... 100 ..... 1010111 @r_vm
 vmadc_vim       010001 . ..... ..... 011 ..... 1010111 @r_vm
-vsbc_vvm        010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
-vsbc_vxm        010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vsbc_vvm        010010 0 ..... ..... 000 ..... 1010111 @r_vm_0
+vsbc_vxm        010010 0 ..... ..... 100 ..... 1010111 @r_vm_0
 vmsbc_vvm       010011 . ..... ..... 000 ..... 1010111 @r_vm
 vmsbc_vxm       010011 . ..... ..... 100 ..... 1010111 @r_vm
 vand_vv         001001 . ..... ..... 000 ..... 1010111 @r_vm
-- 
2.43.0

Re: [PATCH v2 3/3] target/riscv: vadc and vsbc are vm=0 instructions

[Nutty Liu]

On 6/27/2025 9:20 PM, Max Chou wrote:
> From: Anton Blanchard <antonb@tenstorrent.com>
>
> We were marking vadc and vsbc as vm=1 instructions, which meant
> vext_check_input_eew wouldn't detect mask vs source register
> overlaps.
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn32.decode | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index cd23b1f3a9b..5442203ecaa 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -451,14 +451,14 @@ vwsubu_wv       110110 . ..... ..... 010 ..... 1010111 @r_vm
>   vwsubu_wx       110110 . ..... ..... 110 ..... 1010111 @r_vm
>   vwsub_wv        110111 . ..... ..... 010 ..... 1010111 @r_vm
>   vwsub_wx        110111 . ..... ..... 110 ..... 1010111 @r_vm
> -vadc_vvm        010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
> -vadc_vxm        010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
> -vadc_vim        010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
> +vadc_vvm        010000 0 ..... ..... 000 ..... 1010111 @r_vm_0
> +vadc_vxm        010000 0 ..... ..... 100 ..... 1010111 @r_vm_0
> +vadc_vim        010000 0 ..... ..... 011 ..... 1010111 @r_vm_0
>   vmadc_vvm       010001 . ..... ..... 000 ..... 1010111 @r_vm
>   vmadc_vxm       010001 . ..... ..... 100 ..... 1010111 @r_vm
>   vmadc_vim       010001 . ..... ..... 011 ..... 1010111 @r_vm
> -vsbc_vvm        010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
> -vsbc_vxm        010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
> +vsbc_vvm        010010 0 ..... ..... 000 ..... 1010111 @r_vm_0
> +vsbc_vxm        010010 0 ..... ..... 100 ..... 1010111 @r_vm_0
>   vmsbc_vvm       010011 . ..... ..... 000 ..... 1010111 @r_vm
>   vmsbc_vxm       010011 . ..... ..... 100 ..... 1010111 @r_vm
>   vand_vv         001001 . ..... ..... 000 ..... 1010111 @r_vm

Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>

Thanks,
Nutty