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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43890408a66sm191775905e9.5.2025.01.21.10.22.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jan 2025 10:22:11 -0800 (PST) Message-ID: <93f508f5-d38c-4565-be45-eeec3428208a@linaro.org> Date: Tue, 21 Jan 2025 19:22:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] target/riscv/debug.c: use wp size = 4 for 32-bit CPUs To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org References: <20250121170626.1992570-1-dbarboza@ventanamicro.com> <20250121170626.1992570-2-dbarboza@ventanamicro.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250121170626.1992570-2-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 21/1/25 18:06, Daniel Henrique Barboza wrote: > The mcontrol select bit (19) is always zero, meaning our triggers will > always match virtual addresses. In this condition, if the user does not > specify a size for the trigger, the access size defaults to XLEN. > > At this moment we're using def_size = 8 regardless of CPU XLEN. Use > def_size = 4 in case we're running 32 bits. > > Fixes: 95799e36c1 ("target/riscv: Add initial support for the Sdtrig extension") > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/debug.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/debug.c b/target/riscv/debug.c > index f6241a80be..9db4048523 100644 > --- a/target/riscv/debug.c > +++ b/target/riscv/debug.c > @@ -478,7 +478,7 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) > bool enabled = type2_breakpoint_enabled(ctrl); > CPUState *cs = env_cpu(env); > int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; > - uint32_t size; > + uint32_t size, def_size; > > if (!enabled) { > return; > @@ -501,7 +501,9 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) > cpu_watchpoint_insert(cs, addr, size, flags, > &env->cpu_watchpoint[index]); > } else { > - cpu_watchpoint_insert(cs, addr, 8, flags, > + def_size = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4; Reviewed-by: Philippe Mathieu-Daudé