From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCUU7-0007Og-DU for qemu-devel@nongnu.org; Mon, 13 Jun 2016 12:13:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCUU1-0005RI-99 for qemu-devel@nongnu.org; Mon, 13 Jun 2016 12:13:06 -0400 Received: from mail-qg0-x22b.google.com ([2607:f8b0:400d:c04::22b]:35610) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCUU1-0005RD-4J for qemu-devel@nongnu.org; Mon, 13 Jun 2016 12:13:01 -0400 Received: by mail-qg0-x22b.google.com with SMTP id v48so52286438qgd.2 for ; Mon, 13 Jun 2016 09:13:01 -0700 (PDT) Sender: Richard Henderson References: <1465758111-60131-1-git-send-email-mrolnik@gmail.com> From: Richard Henderson Message-ID: <940341be-1efd-5a2f-bc56-af38be1e09ab@twiddle.net> Date: Mon, 13 Jun 2016 09:12:58 -0700 MIME-Version: 1.0 In-Reply-To: <1465758111-60131-1-git-send-email-mrolnik@gmail.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v6 00/11] 8bit AVR cores List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Rolnik , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org On 06/12/2016 12:01 PM, Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. > However I was able to execute simple code with functions. e.g fibonacci calculation. > This series of patches include a non real, sample board. > No fuses support yet. PC is set to 0 at reset. > > the patches include the following > 1. just a basic 8bit AVR CPU, without instruction decoding or translation > 2. CPU features which allow define the following 8bit AVR cores > avr1 > avr2 avr25 > avr3 avr31 avr35 > avr4 > avr5 avr51 > avr6 > xmega2 xmega4 xmega5 xmega6 xmega7 > 3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code > 4. encoding for all AVR instructions > 5. interrupt handling > 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions > 7. a decoder which given an opcode decides what istruction it is > 8. translation of AVR instruction into TCG > 9. all features together > > changes since v3 You should be continuing to add to this list of changes with every revision. At present I'm having to go back and diff this against your previous patch sets, something that most reviewers aren't going to do. You need to keep up with checkpatch.pl warnings: total: 0 errors, 0 warnings, 1214 lines checked total: 0 errors, 0 warnings, 388 lines checked total: 0 errors, 0 warnings, 361 lines checked total: 0 errors, 0 warnings, 762 lines checked total: 0 errors, 0 warnings, 69 lines checked total: 0 errors, 0 warnings, 189 lines checked total: 0 errors, 0 warnings, 693 lines checked total: 2 errors, 0 warnings, 2743 lines checked total: 0 errors, 0 warnings, 203 lines checked total: 4 errors, 4 warnings, 115 lines checked total: 276 errors, 30 warnings, 1285 lines checked r~