From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2ABECC7EE2D for ; Wed, 1 Mar 2023 11:53:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pXL0b-0002cY-7v; Wed, 01 Mar 2023 06:52:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pXL0V-0002bI-Cl; Wed, 01 Mar 2023 06:52:28 -0500 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pXL0S-0000ob-9w; Wed, 01 Mar 2023 06:52:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=MIME-Version:Content-Type:References: In-Reply-To:Date:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=R5GTZfLv+QhslJivvWGoz1hJVAaLsDF8Chkn9o4bXAc=; b=phP/IZlu2W+9BArzHFxiWirVQl Q0jp2Dmq485410pCf493NQHA9zgX0xbh/jw/wpeFB26FuvNDtQFCiL6OCO3Tkt9Ibt++Ec9C/ZxZa KkhDYFk/hJe3QtZjAEaQFvLswXBnTkuoIMpPi+kDS+sHqkNpUrGqmW1tZjCjmwzGRQf7PBvkqxKqn NpMVDdZJzUwlUfCGi8GS6posIPFyXzjtuBacTV9Wesq6bxo00IDQJKOHWtqcuLE4Whi+yT1RkUKyu t4d9BQWItU/9CjrGcPUbuUqmljwlhc3jQFWf1ODJi0dhPVrG9c2Jz0agmZ/U0H5hRNY9Ro0GJaEcj HjGMdxzA==; Received: from [2001:8b0:10b:5:15b6:2526:f3a7:87e2] (helo=u3832b3a9db3152.ant.amazon.com) by casper.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1pXL0B-001bPC-CN; Wed, 01 Mar 2023 11:52:07 +0000 Message-ID: <943866390436e3c8828fea3e8cec117ae8553887.camel@infradead.org> Subject: Re: [PATCH v5 5/7] hw/isa/vt82c686: Work around missing level sensitive irq in i8259 model From: David Woodhouse To: BALATON Zoltan , Bernhard Beschow Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Gerd Hoffmann , Daniel Henrique Barboza , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Date: Wed, 01 Mar 2023 11:52:01 +0000 In-Reply-To: <6502f6bd-029c-25a8-49ec-e61784c64db5@eik.bme.hu> References: <6502f6bd-029c-25a8-49ec-e61784c64db5@eik.bme.hu> Content-Type: multipart/signed; micalg="sha-256"; protocol="application/pkcs7-signature"; boundary="=-k6CtvvObu3p38AfsqtX8" User-Agent: Evolution 3.44.4-0ubuntu1 MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by casper.infradead.org. See http://www.infradead.org/rpr.html Received-SPF: none client-ip=2001:8b0:10b:1236::1; envelope-from=BATV+f4e15e254fb7e3cd38fc+7129+infradead.org+dwmw2@casper.srs.infradead.org; helo=casper.infradead.org X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --=-k6CtvvObu3p38AfsqtX8 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2023-03-01 at 12:27 +0100, BALATON Zoltan wrote: > On Wed, 1 Mar 2023, Bernhard Beschow wrote: > > Am 1. M=C3=A4rz 2023 00:17:11 UTC schrieb BALATON Zoltan : > > > MorphOS sets the ISA PIC to level sensitive mode but QEMU does > > > not > > > support that so this causes a freeze if multiple devices try to > > > raise > > > a shared interrupt. Work around it by lowering the interrupt > > > before > > > raising it again if it is already raised. This could be reverted > > > when > > > the i8259 model is fixed. > > >=20 > > > Signed-off-by: BALATON Zoltan > > > --- > > > hw/isa/vt82c686.c | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > >=20 > > > diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c > > > index 018a119964..3e44a51f92 100644 > > > --- a/hw/isa/vt82c686.c > > > +++ b/hw/isa/vt82c686.c > > > @@ -549,6 +549,7 @@ struct ViaISAState { > > > =C2=A0=C2=A0=C2=A0=C2=A0 PCIDevice dev; > > > =C2=A0=C2=A0=C2=A0=C2=A0 qemu_irq cpu_intr; > > > =C2=A0=C2=A0=C2=A0=C2=A0 qemu_irq *isa_irqs_in; > > > +=C2=A0=C2=A0=C2=A0 uint16_t isa_irqs_state; > > > =C2=A0=C2=A0=C2=A0=C2=A0 ViaSuperIOState via_sio; > > > =C2=A0=C2=A0=C2=A0=C2=A0 MC146818RtcState rtc; > > > =C2=A0=C2=A0=C2=A0=C2=A0 PCIIDEState ide; > > > @@ -636,6 +637,14 @@ static void via_isa_set_pci_irq(void > > > *opaque, int irq_num, int level) > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 pic_level |=3D pci_bus_get_irq_level(bus, i); > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > > > =C2=A0=C2=A0=C2=A0=C2=A0 } > > > +=C2=A0=C2=A0=C2=A0 /* FIXME: workaround for i8259: level sensitive i= rq not > > > supported */ > > > +=C2=A0=C2=A0=C2=A0 if ((s->isa_irqs_state & BIT(pic_irq)) && pic_lev= el) { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 qemu_irq_lower(s->isa_irq= s_in[pic_irq]); > > > +=C2=A0=C2=A0=C2=A0 } else if (pic_level) { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 s->isa_irqs_state |=3D BI= T(pic_irq); > > > +=C2=A0=C2=A0=C2=A0 } else { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 s->isa_irqs_state &=3D ~B= IT(pic_irq); > > > +=C2=A0=C2=A0=C2=A0 } > >=20 > > Let's not clutter the device model with workarounds which quickly > > snowball into unmaintainable code. Please fix the i8259 instead. >=20 > Do you have an idea how?=20 Let's start by understanding the problem completely. The i8259 *does* support level-triggered interrupts. Look at the checks for s->elcr in hw/intc/i8259.c, in pic_set_irq()... if (s->elcr & mask) { /* level triggered */ if (level) { s->irr |=3D mask; s->last_irr |=3D mask; } else { s->irr &=3D ~mask; s->last_irr &=3D ~mask; } } else { /* edge triggered */ ... and in pic_intack() ... /* We don't clear a level sensitive interrupt here */ if (!(s->elcr & (1 << irq))) { s->irr &=3D ~(1 << irq); } What qemu typically has an issue with is *shared* level-triggered interrupts. But that would cause a level to be "forgotten" if another input asserts and then deasserts the IRQ while one input thinks it's holding it asserted. And I don't see how your workaround above would have helped in that situation. Are you sure the PIC ELCR is actually set for the lines you're having trouble with? Is that something the Pegasos SmartFirmware would have done, and MorphOS is expecting to inherit but isn't actually setting up for itself? --=-k6CtvvObu3p38AfsqtX8 Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCEkQw ggYQMIID+KADAgECAhBNlCwQ1DvglAnFgS06KwZPMA0GCSqGSIb3DQEBDAUAMIGIMQswCQYDVQQG EwJVUzETMBEGA1UECBMKTmV3IEplcnNleTEUMBIGA1UEBxMLSmVyc2V5IENpdHkxHjAcBgNVBAoT FVRoZSBVU0VSVFJVU1QgTmV0d29yazEuMCwGA1UEAxMlVVNFUlRydXN0IFJTQSBDZXJ0aWZpY2F0 aW9uIEF1dGhvcml0eTAeFw0xODExMDIwMDAwMDBaFw0zMDEyMzEyMzU5NTlaMIGWMQswCQYDVQQG EwJHQjEbMBkGA1UECBMSR3JlYXRlciBNYW5jaGVzdGVyMRAwDgYDVQQHEwdTYWxmb3JkMRgwFgYD VQQKEw9TZWN0aWdvIExpbWl0ZWQxPjA8BgNVBAMTNVNlY3RpZ28gUlNBIENsaWVudCBBdXRoZW50 aWNhdGlvbiBhbmQgU2VjdXJlIEVtYWlsIENBMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKC 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