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([2602:47:d49d:ec01:142b:b2fd:5c12:7cf3]) by smtp.gmail.com with ESMTPSA id f16-20020a635550000000b004299489dd2bsm4599925pgm.8.2022.08.20.10.33.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Aug 2022 10:33:39 -0700 (PDT) Message-ID: <949fb9c0-8e7f-d0bd-dbfa-e76067b867d8@linaro.org> Date: Sat, 20 Aug 2022 10:33:37 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220811171619.1154755-1-peter.maydell@linaro.org> <20220811171619.1154755-9-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220811171619.1154755-9-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/11/22 10:16, Peter Maydell wrote: > FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD, > which disable the cycle counter from counting at EL2 and EL3. > Add the code to support these bits. While HCCD is v3p5, it seems MCCD (typo above) is v3p7. > + if (counter == 31) { > + /* > + * The cycle counter defaults to running. PMCR.DP says "disable > + * the cycle counter when event counting is prohibited". > + * Some MDCR bits disable the cycle counter specifically. > + */ > + prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; > + if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { > + if (el == 3) { > + prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_MCCD); > + } else if (el == 2) { > + prohibited = prohibited || (mdcr_el2 & MDCR_HCCD); > + } But modulo the feature test, the behaviour looks right. r~