From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JJYhe-0001ea-1n for qemu-devel@nongnu.org; Mon, 28 Jan 2008 13:27:30 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JJYhc-0001db-5A for qemu-devel@nongnu.org; Mon, 28 Jan 2008 13:27:29 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JJYhb-0001dY-SG for qemu-devel@nongnu.org; Mon, 28 Jan 2008 13:27:27 -0500 Received: from wx-out-0506.google.com ([66.249.82.224]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1JJYhb-0007X9-GC for qemu-devel@nongnu.org; Mon, 28 Jan 2008 13:27:27 -0500 Received: by wx-out-0506.google.com with SMTP id h31so1160127wxd.4 for ; Mon, 28 Jan 2008 10:27:21 -0800 (PST) Message-ID: <94a0d4530801281027u4db7bd2eib4e7d5f9c6caeb8b@mail.gmail.com> Date: Mon, 28 Jan 2008 20:27:20 +0200 From: "Felipe Contreras" Subject: Re: [Qemu-devel] [PATCH] arm eabi TLS In-Reply-To: <1197508540.3640.2.camel@phantasm.home.enterpriseandprosperity.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <1197420297.2947.94.camel@phantasm.home.enterpriseandprosperity.com> <476068AA.80001@bellard.org> <200712130121.04204.paul@codesourcery.com> <1197508540.3640.2.camel@phantasm.home.enterpriseandprosperity.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: thayne@c2.net, qemu-devel@nongnu.org Cc: Paul Brook On Dec 13, 2007 3:15 AM, Thayne Harbaugh wrote: > > > On Thu, 2007-12-13 at 01:21 +0000, Paul Brook wrote: > > > - It would be good to limit the changes in the CPU emulation code to > > > handle the TLS. For example, on MIPS, the TLS register must not be > > > stored in the CPU state. Same for ARM. > > > > I disagree. The TLS register is part of the CPU state. On many machines > > (including ARMv6 CPUs) it's an actual CPU register. I'm fairly sure the same > > is true for recent MIPS revisions. > > I agree with Paul. Some archs actually use a CPU register and require > the kernel to help manage TLS. Other archs can manage TLS completely in > user space. It's been a while since I've investigated all the details > for each arch but I'll go review it. How is this going? The patch works pretty well for me. -- Felipe Contreras