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[176.184.10.225]) by smtp.gmail.com with ESMTPSA id f2-20020a170906390200b00988cfb8ccd4sm1089902eje.142.2023.06.19.08.49.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Jun 2023 08:49:01 -0700 (PDT) Message-ID: <94a453bc-cfd5-5fb0-289d-dbb321c8b172@linaro.org> Date: Mon, 19 Jun 2023 17:48:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 2/4] target/ppc: Ensure stcx size matches larx Content-Language: en-US To: Nicholas Piggin , Daniel Henrique Barboza Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org, Peter Maydell References: <20230604102858.148584-1-npiggin@gmail.com> <20230604102858.148584-2-npiggin@gmail.com> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/5/23 08:27, Nicholas Piggin wrote: > On Sun Jun 4, 2023 at 8:28 PM AEST, Nicholas Piggin wrote: >> Differently-sized larx/stcx. pairs can succeed if the starting address >> matches. Add a size check to require stcx. exactly match the larx that >> established the reservation. > > Hmm, question: reserve_addr is a VMSTATE field, but reserve_val is not > (nor reserve_size after this patch). > > Blue Swirl added that with commit a456d59c20f ("VM load/save support for > PPC CPU"), and when reserve_val was added in commit 18b21a2f83a > ("target-ppc: retain l{w,d}arx loaded value") it did not get migrated. > > Could we end up with reserve_addr != -1, but with a bogus reserve_val, > which could then permit a stcx. incorrectly? Not entirely outlandish if > reserve_val starts out initialised to zero. > > Could we just clear the reserve in cpu_post_load? It is permitted to be > lost for an implementation-specific reason. Doesn't seem necessary to > try keep it alive over a migration. It's not a bad idea to flush the reservation over migrate. You can do - VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), + VMSTATE_UNUSED(sizeof(target_long)) when making that change. Peter, any thoughts on this? If we're going to do one guest, we might ought to do the same for all load-lock/store-conditional guests. r~