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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-212878b7046sm1263195ad.107.2024.11.20.15.48.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Nov 2024 15:48:16 -0800 (PST) Message-ID: <94d13e1f-aeaa-4d17-bc51-469e14d3a8ca@linaro.org> Date: Wed, 20 Nov 2024 15:48:16 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Status of some Arm features Content-Language: en-US To: Peter Maydell Cc: "qemu-devel@nongnu.org" , =?UTF-8?Q?Alex_Benn=C3=A9e?= , Richard Henderson References: <51442716-467b-46c2-b2f7-8ffdeeca320e@linaro.org> From: Pierrick Bouvier In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/19/24 02:54, Peter Maydell wrote: > On Tue, 19 Nov 2024 at 10:09, Peter Maydell wrote: >> >> On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier wrote: >>> 8.4: >>> - FEAT_CNTSC, Generic Counter Scaling (hw/timer/sse-counter.c) >> >> This is optional, and we don't implement it yet. (There's an >> open ticket for it in Linaro JIRA at >> https://linaro.atlassian.net/browse/QEMU-309 ) > > Oh, and I didn't notice you mentioning sse-counter.c here. > That source file is for an M-profile device, which performs > a similar function to but is not the same as the A-profile > memory-mapped counter which FEAT_CNTSC is an extension for. > > The A-profile memory-mapped counter is technically architecturally > required but in practice none of the guest software we're > running on the board models we implement cares about it. > > We don't model the A-profile memory mapped counter, because > so far we haven't had a real need to. Modelling this is not > completely trivial, because in a system with the memory > mapped architectural counter/timer modules, all the CPU > generic timers (accessed via system registers) are supposed > to take their source of time from the memory-mapped > counter (and so for instance if you write to the memory mapped > counter to stop it from counting then the CPU generic timers > also must stop counting). So you need something similar to > what I implemented in sse-counter.c where it provides an > interface that other timer devices can use to consume its > count (sse_counter_register_consumer(), sse_counter_for_timestamp(), > sse_counter_tick_to_time() -- these are used by the M-profile > hw/timer/sse-timer). > > I do actually have a hacked-together prototype of this for > A-profile that I did for something a while back, but it's not > really in a state to be able to post upstream currently > (I just did the bits I needed and didn't really finish it > out or test it very much). So if we need this (e.g. if > we decide it makes sense to implement in the sbsa-ref > board) we could do it. But there doesn't really seem to > be any requirement to do this work right now. > Thanks for the insight Peter, it's very helpful to understand. > -- PMM