Re: [Qemu-devel] [PATCH v2 4/4] target-tricore: Added new JNE instruction variant

[Bastian Koppelmann <kbastian@mail.uni-paderborn.de>]

On 05/31/2016 07:49 AM, peer.adelt@c-lab.de wrote:
> From: Peer Adelt <peer.adelt@c-lab.de>
> 
> If D[15] is != sign_ext(const4) then PC will be set to (PC +
> zero_ext(disp4 + 16)).
> 
> Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
> ---
>  target-tricore/translate.c       | 11 +++++++++++
>  target-tricore/tricore-opcodes.h |  1 +
>  2 files changed, 12 insertions(+)
> 
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index 960ee33..21732f8 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -3363,6 +3363,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
>          gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
>          break;
>      case OPC1_16_SBC_JNE:
> +    case OPC1_16_SBC_JNE16:
>          gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
>          break;
>  /* SBRN-format jumps */
> @@ -4097,6 +4098,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
>          const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
>          gen_compute_branch(ctx, op1, 0, 0, const16, address);
>          break;
> +    case OPC1_16_SBC_JEQ16:


This doesn't compile since OPC1_16_SBC_JEQ16 is not defined. Remove this
or better implement JEQ16 as well since both insn are similar.

Also, if you resend a patches always resend the whole series and add the
reviewed-by tags to the commit messages of already reviewed patches.

Cheers,
   Bastian