From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7fHp-00068v-LQ for qemu-devel@nongnu.org; Tue, 31 May 2016 04:44:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b7fHk-00077z-MT for qemu-devel@nongnu.org; Tue, 31 May 2016 04:44:28 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:58178) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7fHk-00077f-FO for qemu-devel@nongnu.org; Tue, 31 May 2016 04:44:24 -0400 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.84_2 zuban) id 1b7fHh-000101-M3 for qemu-devel@nongnu.org; Tue, 31 May 2016 10:44:22 +0200 Received: from mail.uni-paderborn.de by pova with queue id 1137542-2 for qemu-devel@nongnu.org; Tue, 31 May 2016 08:44:21 GMT References: <1464673745-14628-1-git-send-email-peer.adelt@c-lab.de> From: Bastian Koppelmann Message-ID: <95000d30-76a9-bd8c-c1cb-7a95df05dbd7@mail.uni-paderborn.de> Date: Tue, 31 May 2016 10:44:20 +0200 MIME-Version: 1.0 In-Reply-To: <1464673745-14628-1-git-send-email-peer.adelt@c-lab.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 4/4] target-tricore: Added new JNE instruction variant List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peer.adelt@c-lab.de, qemu-devel@nongnu.org On 05/31/2016 07:49 AM, peer.adelt@c-lab.de wrote: > From: Peer Adelt > > If D[15] is != sign_ext(const4) then PC will be set to (PC + > zero_ext(disp4 + 16)). > > Signed-off-by: Peer Adelt > --- > target-tricore/translate.c | 11 +++++++++++ > target-tricore/tricore-opcodes.h | 1 + > 2 files changed, 12 insertions(+) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index 960ee33..21732f8 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -3363,6 +3363,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, > gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); > break; > case OPC1_16_SBC_JNE: > + case OPC1_16_SBC_JNE16: > gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); > break; > /* SBRN-format jumps */ > @@ -4097,6 +4098,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) > const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); > gen_compute_branch(ctx, op1, 0, 0, const16, address); > break; > + case OPC1_16_SBC_JEQ16: This doesn't compile since OPC1_16_SBC_JEQ16 is not defined. Remove this or better implement JEQ16 as well since both insn are similar. Also, if you resend a patches always resend the whole series and add the reviewed-by tags to the commit messages of already reviewed patches. Cheers, Bastian