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Tue, 7 Jul 2020 09:17:33 +0000 (UTC) Subject: Re: [PATCH] intel_iommu: Use correct shift for 256 bits qi descriptor To: Liu Yi L , peterx@redhat.com References: <1593850035-35483-1-git-send-email-yi.l.liu@intel.com> From: Jason Wang Message-ID: <953608d9-16dc-aa2a-4016-a12fdfd9cc66@redhat.com> Date: Tue, 7 Jul 2020 17:17:32 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <1593850035-35483-1-git-send-email-yi.l.liu@intel.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=jasowang@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=207.211.31.81; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/07 00:20:54 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, mst@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2020/7/4 下午4:07, Liu Yi L wrote: > In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced > in VTD_IQA_REG. Sfotware could set this bit to tell VT-d the QI descriptor Typo. > from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should > be 5 when descriptor size is 256 bits. > > This patch adds the DW bit check when deciding the shift used to update > VTD_IQH_REG. > > Signed-off-by: Liu Yi L Acked-by: Jason Wang > --- > hw/i386/intel_iommu.c | 7 ++++++- > hw/i386/intel_iommu_internal.h | 3 ++- > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index df7ad25..8703a2d 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -2549,6 +2549,11 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) > /* Try to fetch and process more Invalidation Descriptors */ > static void vtd_fetch_inv_desc(IntelIOMMUState *s) > { > + int qi_shift; > + > + /* Refer to 10.4.23 of VT-d spec 3.0 */ > + qi_shift = s->iq_dw ? VTD_IQH_QH_SHIFT_5 : VTD_IQH_QH_SHIFT_4; > + > trace_vtd_inv_qi_fetch(); > > if (s->iq_tail >= s->iq_size) { > @@ -2567,7 +2572,7 @@ static void vtd_fetch_inv_desc(IntelIOMMUState *s) > } > /* Must update the IQH_REG in time */ > vtd_set_quad_raw(s, DMAR_IQH_REG, > - (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) & > + (((uint64_t)(s->iq_head)) << qi_shift) & > VTD_IQH_QH_MASK); > } > } > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 862033e..3d5487f 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -230,7 +230,8 @@ > #define VTD_IQA_DW_MASK 0x800 > > /* IQH_REG */ > -#define VTD_IQH_QH_SHIFT 4 > +#define VTD_IQH_QH_SHIFT_4 4 > +#define VTD_IQH_QH_SHIFT_5 5 > #define VTD_IQH_QH_MASK 0x7fff0ULL > > /* ICS_REG */